### PERFORMANCE ANALYSIS AND OPTIMIZATION OF 10 NM TG N- AND P-CHANNEL SOI FINFETS FOR CIRCUIT APPLICATIONS

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#### Abstract

_{TH}, the subthreshold swing (SS), the transconductance and the on/off current ratio, I

_{ON}/I

_{OFF}, is investigated. The two structures have been optimized for CMOS inverter implementation. The simulation results show that the N-FinFET and the P-FinFET can reach a minimum SS value with Fin heights of 15 nm and 9 nm, respectively. In addition, low threshold voltages of 0.61 V and 0.27 V for N- and P-channel SOI FinFETs, respectively, are obtained at a Fin width of 7 nm.

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