Shiva Prasad Das, Ananya Dastidar, Partha Sarkar, Sushanta Kumar Mohapatra

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Investigation of mixed mode performances for GaAs UTB-MOSFET at nanoscale regime keeping in view of “Beyond CMOS” is the current trend of semiconductor industry. Here it is proposed to modify conventional models by considering an extra Insulator Region (IR) and Undoped Buried oxide Region (UBR) to study the performance related to digital and analog/RF applications. Here a GaAs is considered as the channel material. The IR-UTB-SOI-n-MOSFET has shown promising results with respect to SS, DIBL, fT and switching speed.


Silicon-On-Insulator, UTB MOSFET, GaAs, DIBL, Analog/RF Performance, Insulator Region

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S. Cristoloveanu, “Silicon on insulator technologies and devices: from present to future,” Solid. State. Electron., vol. 45, no. 8, pp. 1403–1411, 2001.

M. A. Pavanello, J. A. Martino, V. Dessard, and D. Flandre, “Analog performance and application of graded-channel fully depleted SOI MOSFETs,” Solid. State. Electron., vol. 44, no. 7, pp. 1219–1222, 2000.

K. Kim, “1.1 Silicon technologies and solutions for the data-driven world,” In Digest of Technical Papers 2015 IEEE International Solid-State Circuits Conference-(ISSCC), 2015, pp. 1–7.

J.-T. Park and J.-P. Colinge, “Multiple-gate SOI MOSFETs: device design guidelines,” Electron Devices, IEEE Trans., vol. 49, no. 12, pp. 2222–2229, 2002.

A. Chaudhry and M. J. Kumar, “Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET,” Electron Devices, IEEE Trans., vol. 51, no. 9, pp. 1463–1467, 2004.

S. Cristoloveanu and S. Li, Electrical characterization of silicon-on-insulator materials and devices, vol. 305. Springer Science & Business Media, 2013.

B. Vandana, “Study of Floating Body Effect in SOI Technology,” Int. J. Mod. Eng. Res., vol. 3, no. June, pp. 1817–1824, 2013.

S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “ZTC bias point of advanced fin based device: The importance and exploration,” Facta Univiversitatis: Series, Electronics and Energetics, vol. 28, no. 3, pp. 393–405, 2015.

Q. Xie, C.-J. Lee, J. Xu, C. Wann, J. Y.-C. Sun, and Y. Taur, “Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs,” Electron Devices, IEEE Trans., vol. 60, no. 6, pp. 1814–1819, 2013.

H.-S. Wong, “Beyond the conventional transistor,” IBM J. Res. Dev., vol. 46, no. 2.3, pp. 133–168, 2002.

R. H. Reuss et al., “Macroelectronics: Perspectives on technology and applications,” Proc. IEEE, vol. 93, no. 7, pp. 1239–1256, 2005.

J. Yoon et al., “GaAs photovoltaics and optoelectronics using releasable multilayer epitaxial assemblies,” Nature, vol. 465, no. 7296, pp. 329–333, 2010.

A. A. Orouji and M. K. Anvarifard, “SOI MOSFET with an insulator region (IR-SOI): A novel device for reliable nanoscale CMOS circuits,” Mater. Sci. Eng. B, pp. 1–7, 2013.

M. Rahimian and A. A. Orouji, “A novel nanoscale MOSFET with modified buried layer for improving of AC performance and self-heating effect,” Mater. Sci. Semicond. Process., vol. 15, no. 4, pp. 445–454, 2012.

Atlas User Manual. Silvaco International,Santa Clara, 2012.

H. A. El Hamid, J. R. Guitart, and B. Iñíguez, “Two-dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double-gate MOSFETs,” Electron Devices, IEEE Trans., vol. 54(6), p. 1402–1408., 2007.

J. P. Colinge, “Multiple-gate SOI MOSFETs,” Solid State Electron, vol. 48 (6), pp. 897–905, 2004.

“The International Technology Roadmap for Semiconductors,” 2011.

S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics,” Superlattices Microstruct., vol. 78, pp. 134–143, 2015.

S. Chakraborty, A. Mallik, and C. K. Sarkar, “Subthreshold performance of dual-material gate CMOS devices and circuits for ultralow power analog/mixed-signal applications,” Electron Devices, IEEE Trans., vol. 55 (3), pp. 827–832, 2008.

W. Shockley and W. T. Read, “Statistics of the recombination of holes and electrons,” Phys. Rev., vol. 87, pp. 835–842, 1952.

R. N. Hall, “Electron–hole recombination in germanium,” Phys. Rev., vol. Phys. Rev., p. 387, 1952.

C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, “A physically based mobility model for numerical simulation of nonplanar devices,” IEEE Trans. Comput. Des. Integr. Circ. Syst., vol. 7 (11), pp. 1164–1171, 1988.

P. K. Sahu, S. K. Mohapatra, and K. P. Pradhan, “Zero temperature-coefficient bias point over wide range of temperatures for single- and double-gate UTB-SOI n-MOSFETs with trapped charges,” Mater. Sci. Semicond. Process., vol. 31, pp. 175–183, 2015.

S. Selberherr, “Analysis and Simulation of Semiconductor Devices,” Springer–Verlag, Wien–NewYork, 1984.

G. C. Patil and S. Qureshi, “Impact of Segregation Layer on Scalability and Analog / RF Performance of Nanoscale Schottky Barrier,” J. Semicond. Technol. Sci., vol. 12, no. 1, pp. 66–74, 2012.

K. P. Pradhan, D. Singh, S. K. Mohapatra, and P. K. Sahu, “Assessment of III-V FinFETs at 20 nm node: A Process variation analysis,” Procedia Comput. Sci., vol. 57, pp. 454–459, 2015.


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