MEMORY CHIPS AND UNITS RADIATION TOLERANCE DEPENDENCE ON SUPPLY VOLTAGE DURING IRRADIATION AND TEST

Andrey G. Petrov, Aleksander Y. Nikiforov, Anna B. Boruzdina, Anastasia V. Ulanova, Andrey V. Yanenko

DOI Number
https://doi.org/10.2298/FUEE1801131P
First page
131
Last page
140

Abstract


In this work we investigate the influence of various memory chips supply voltage on their sensitivity to the radiation environment. The main physical mechanisms responsible for radiation-induced degradation at nominal, increased, and decreased supply voltage values are discussed. It is demonstrated that, depending on supply voltage value during irradiation and subsequent testing, device's tolerance to data corruption effects in memory circuits, single event latch-up (SEL) and hard errors induced by ionizing radiation can vary significantly. We also give some recommendations to perform radiation tests.


Keywords

space radiation, memory, digital integrated circuits, flash, SRAM, SEU, total dose

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References


P. Nekrasov, A. Demidov, O. Kalashnikov, “Functional checks of microprocessors during radiation tests”, Instruments and Experimental Techniques, vol. 52, no. 2, pp. 196-199, 2009.

O. Kalashnikov, A. Demidov, V. Figurov, A. Nikiforov, S. Polevich, V. Telets, S. Maljudin, A. Artamonov “Integrating analog-to-digital converter radiation hardness test technique and results”, IEEE Transactions on Nuclear Science, 1998, vol. 45, no. 6 (1), pp. 2611-2615, 1998.

A. Boruzdina, A. Ulanova, N. Grigor'ev, A. Nikiforov, “Radiation-induced degradation in the dynamic parameters of memory chips”, Russian Microelectronics, vol. 41, no. 4, pp. 259-265, 2002.

O. Kalashnikov, “Statistical Variations of Integrated Circuits Radiation Hardness”, In Proceedings of the RADECS Conference, 2011, pp. 661-665.

O. Kalashnikov, “CMOS Integrated Circuits Total Dose Functional Upset Sensitivity to Operation Mode”, In Proceedings of the 4th Workshop on Electronics for LHC Experiments, 1998, Rome, Italy, pp. 484-485.

A. Kirgizova, A. Nikiforov, N. Grigor'ev, I. Poljakov, P. Skorobogatov, “Dominant mechanisms of transient-radiation upset in CMOS RAM VLSI circuits realized in SOS technology”, Russian Microelectronics, vol. 35, no. 3, pp. 162-176, 2006.

A. Karakozov, O. Korneev, P. Nekrasov, P. Nekrasov, M. Sokolov, D. Zagryadsky, “Bias conditions and functional test procedure influence on PowerPC7448 microprocessor TID tolerance”, In Proceedings of the RADECS Conference, 2013. pp. 1-2.

D. Bobrovsky, O. Kalashnikov, P. Nekrasov, “Functional control technique for FPGA total ionizing dose testing”, In Proceedings of the RADECS Conference, 2012.

O. Kalashnikov, A. Artamonov, A. Demidov, “ADC/DAC Radiation Test Technique”, Workshop Record 4th European Conf. "Radiations and Their Effects on Devices and Systems" In Proceedings of the RADECS Conference, Palm Beach-Cannes, France, 1997, pp. 56-60.

V.A. Marfin, P.V. Nekrasov, and I.O. Loskutov, “Connection of the parametric and functional control for TID testing of complex VLSI circuit,” In Proceedings of the 14th European Conf. on Radiation and its Effects on Components and Systems, RADECS-2015, Moscow; Russian Federation; Sept. 14 -18, 2015, article number 7365664.

I.O. Loskutov, A.B. Karakozov, P.V. Nekrasov, and A.Y. Nikiforov, “Automated radiation test setup for functional and parametrical control of 8-bit microcontrollers,” In Proceedings of the 2015 International Siberian Conference on Control and Communications, SIBCON 2015 Omsk; Russian Federation; May 21 -23, 2015, article number 7147128.

O.A. Kalashnikov, and A.Y. Nikiforov, “TID behavior of complex multifunctional VLSI devices,” In Proceedings of the 29th International Conference on Microelectronics, MIEL 2014, Belgrade, Serbia, May 2014, pp. 455-458.

D. Boychenko, O. Kalashnikov, A. Nikiforov, A. Ulanova, D. Bobrovsky, P. Nekrasov, “Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices”, Facta Universitatis, Series: Electronics and Energetics, vol. 28, Issue 1, pp. 153-164, 2015.

A. Sogoyan, A. Artamonov, A. Nikiforov, D. Boychenko, “Method for integrated circuits total ionizing dose hardness testing based on combined gamma- and x-ray irradiation facilities”, Facta Universitatis, Series: Electronics and Energetics, vol. 27, Issue 3, pp. 329-338, 2014.

T.R. Oldham and F.B. McLean, “Total Ionizing Dose Effects in MOS Oxides and Devices”, IEEE Transaction on Nuclear Science, vol. 50, no. 3, pp. 483-499, June 2003.

A.I. Chumakov, A.L. Vasil'ev, A.A. Kozlov, D.O. Kol'tov, A.V. Krinitskii, A.A. Pechenkin, A.S. Tararaksin, and A.V. Yanenko, “Single-event-effect prediction for ICs in a space environment,” Russian Microelectronics, vol. 39, no. 2, pp. 74-78, 2010.

A. I. Chumakov, A. A. Pechenkin, D. V. Savchenkov, A. S. Tararaksin, A. L. Vasil'ev, and A. V. Yanenko, “Local laser irradiation technique for SEE testing of ICs”, In Proceedings of the 12th European Conf. on Radiation and its Effects on Components and Systems, RADECS-2011, Sevilla; Spain; Sept. 19 -23, 2011, pp. 449-453.

A.I. Chumakov, “Evaluation of multibit upsets in integrated circuits under heavy charged particles,” Russian Microelectronics, vol. 43, no. 2, 2014, pp. 91-95.

A.B. Boruzdina, A.V. Ulanova, A.G. Petrov, V.A. Telets, P. Reviriego and J.A. Maestro, “Verification of SRAM MCUs calculation technique for experiment time optimization,” In Proceedings of the 14th European Conf. on Radiation and its Effects on Components and Systems, RADECS-2013, Oxford; United Kingdom; Sept. 23 -27, article number 6937393.

D.V. Savchenkov, A.I. Chumakov, A.G. Petrov, A.A. Pechenkin, A.N. Egorov, O.B. Mavritskii, and A.V. Yanenko, “Study of SEL and SEU in SRAM using different laser techniques” In Proceedings of the 14th European Conf. on Radiation and its Effects on Components and Systems, RADECS-2013, Oxford; United Kingdom; Sept. 23 -27, article number 6937411.

Z. Zhang, J Liu, Y. Sun, M. Hou, T. Tong, S. Gu, T. Liu, "Supply voltage dependence of single event upset sensitivity in diverse SRAM devices," In Proceedings of the 10th International Conference on Reliability, Maintainability and Safety (ICRMS), Guangzhou, 2014, pp. 114-119.

J. Barak, J. Levinson, A. Akkerman, E. Adler, A. Zentner; D. David, Y. Lifshitz, M. Hass, B.E. Fischer, M. Schlogl, M. Victoria, W. Hajdas, “Scaling of SEU mapping and cross section, and proton induced SEU at reduced supply voltage,” IEEE Transactions on Nuclear Science, vol. 46, no.6, pp. 1342-1353, Dec. 1999.

P. Hazucha, K. Johansson, C. Svensson, “Neutron induced soft errors in CMOS memories under reduced bias,” IEEE Transactions on Nuclear Science, vol.45, no.6, pp.2921-2928, Dec 1998.

A.G. Petrov, A.L. Vasil'ev, A.V. Ulanova, A.I. Chumakov, and A.Y. Nikiforov, “Flash memory cells data loss caused by total ionizing dose and heavy ions,” Central European Journal of Physics, vol. 12, no. 10, pp. 725-729, 2014.

G. Boselli, V. Reddy and C. Duvvury, "Latch-up in 65nm CMOS technology: a scaling perspective," In Proceedings of the IEEE International Reliability Physics Symposium (IRPS2005), 2005, pp. 137-144.

R. Koga, S.J. Hansel, W.R. Crain, K.B. Crawford, S.D. Pinkerton, and J. Quan, “Single Event Upset and Latchup Considerations for CMOS Devices Operated at 3.3 Volts”, Aerospace report no. TR-94(4940)-9, 1995.


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