B Vandana, Jitendra Kumar Das, Sushanta K. Mohapatra, Suman Lata Tripathi

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The paper explores the analog analysis and higher order derivatives of drain current (ID) at gate source voltage (VGS), by introducing channel engineering technique of 3D conventional and Wavy Junctionless FinFETs (JLT) as silicon germanium  (Si1-0.25Ge0.25) device layer. In view of this, the performances are carried out for different gate length (LG) values (15-30 nm) and current characteristics determined by maintaining constant ON current (ION 10-5) (A/μm) for both devices. With respect to this, a comparison has been made between these MOS structures at molefraction x = 0.25 and it was found that the electric field is perpendicular to the current flow which induces volume inversion approach. Accordingly, for the simulation study better channel controllability over the gate is observed for Wavy structures and high ID induces as the LG scales down. With respect to this the constant ION determine ID, transconductance (gm), transconductance generation factor (TGF) and its higher order terms (g\m, and g\\m) of the devices are studied with relaxed SiGe approximation. The extensive simulation study on short channel (SC) parameters are also performed and it is observed that the Wavy JL FinFET shows less sensitivity towards short channel effects (SCEs) over conventional one, therefore the dependency of N-type doping concentration (ND = 1.7x1019 cm-3) and metal workfunction (ϕM = 4.6 eV) are responsible to achieving reduced SCEs.  


SiGe JL FinFET, channel engineering, molefraction, analog parameters, higher order derivatives, short channel parameters (SC)

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C. Hu, “Finfet and other new transistor technologies. Univ. of California. article. Finfet and other new transistor technologies,” 2011.

X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, and others, “Sub 50-nm finfet: Pmos,” in Technical Digest. International of the Electron Devices Meeting, IEDM’99., 1999, pp. 67–70.

D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320–2325, 2000.

S.-Y. Kim and J. H. Lee, “Hot carrier-induced degradation in bulk FinFETs,” IEEE Electron Device Lett., vol. 26, no. 8, pp. 566–568, 2005.

T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horiguchi, Y. Ono, Y. Takahashi, and K. Murase, “Ultimately thin double-gate SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 830–838, 2003.

J. P. Colinge, “The new generation of SOI MOSFETs,” Rom. J. Inf. Sci. Technol, vol. 11, no. 1, pp. 3–15, 2008.

T. Rudenko, S. Barraud, Y. M. Georgiev, V. Lysenko, and A. Nazarov, “Electrical Characterization and Parameter Extraction of Junctionless Nanowire Transistors.,” J. Nano Res., vol. 39, 2016.

J.-P. Colinge, C. W. Lee, A. Afzalian, N. Dehdashti, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, and others, “SOI gated resistor: CMOS without junctions,” in Proceedings of the IEEE International SOI Conference, 2009, pp. 1–2.

A. Kranti, R. Yan, C. W. Lee, I. Ferain, R. Yu, N. D. Akhavan, P. Razavi, and J. P. Colinge, “Junctionless nanowire transistor (JNT): Properties and design guidelines,” in Proceedings of the ESSDERC Conference, 2010, pp. 357–360.

R. Rios, A. Cappellani, M. Armstrong, A. Budrevich, H. Gomez, R. Pai, N. Rahhal-Orabi, and K. Kuhn, “Comparison of junctionless and conventional trigate transistors with Lg down to 26 nm,” IEEE Electron Device Lett., vol. 32, no. 9, pp. 1170–1172, 2011.

B. Vandana, B. S. Patro, S. K. Mohapatra, and J. K. Das, “Exploration towards Electrostatic Integrity for SiGe on Insulator (SG-OI) on Junctionless Channel transistor (JLCT),” Facta Universitatis, Series: Electronics and Energetics, vol. 30, no. 3, pp. 383-390, 2017.

B. Vandana, B. S. Patro, J. K. Das, and S. K. Mohapatra, “Physical insight of junctionless transistor with simulation study of Strained channel,” ECTI Trans. Electr. Eng. Electron. Commun., vol. 15, no. 1, pp. 1–7, 2017.

P. Ghosh, S. Haldar, R. S. Gupta, and M. Gupta, “An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design,” IEEE Trans. Electron Devices, vol. 59, no. 12, pp. 3263–3268, 2012.

Y. Pratap, S. Haldar, R. S. Gupta, and M. Gupta, “Performance evaluation and reliability issues of junctionless CSG MOSFET for RFIC design,” IEEE Trans. Device Mater. Reliab., vol. 14, no. 1, pp. 418–425, 2014.

S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Linearity and analog performance analysis in GSDG-MOSFET with gate and channel engineering,” in Proceedings of the Annual IEEE India Conference (INDICON), 2014, pp. 1–5.

B. Razavi and R. Behzad, RF microelectronics, vol. 2. Prentice Hall New Jersey, 1998.

J.-T. Park and J.-P. Colinge, “Multiple-gate SOI MOSFETs: device design guidelines,” IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2222–2229, 2002.

S. K. Mohapatra, “Investigation on Performance Metrics of Nanoscale Multigate MOSFETs towards RF and IC Applications,” 2015.

F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance,” IEEE Electron Device Lett., vol. 8, no. 9, pp. 410–412, 1987.

L. Mathew, M. Sadd, S. Kalpat, M. Zavala, T. Stephens, R. Mora, S. Bagchi, C. Parker, J. Vasek, and D. Sing, “Inverted T channel FET (ITFET)-Fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel technology for 45nm and beyond CMOS.,” in Technical Digest IEEE International Electron Devices Meeting, IEDM ., 2005, pp. 713–716.

W. Zhang, J. G. Fossum, and L. Mathew, “The ITFET: A novel FinFET-based hybrid device,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2335–2343, 2006.

A. N. Hanna, M. T. Ghoneim, R. R. Bahabry, A. M. Hussain, and M. M. Hussain, “Zinc oxide integrated area efficient high output low power wavy channel thin film transistor,” Appl. Phys. Lett., vol. 103, no. 22, p. 224101, 2013.

A. N. Hanna, A. M. Hussain, and M. M. Hussain, “Wavy Channel architecture thin film transistor (TFT) using amorphous zinc oxide for high-performance and low-power semiconductor circuits,” in Proceedings of the 73rd Annual Device Research Conference (DRC), 2015, pp. 201–202.

K. P. Pradhan, P. K. Sahu, and R. Ranjan, “Investigation on asymmetric dual-k spacer (ADS) Trigate Wavy FinFET: A novel device,” in Proceedings of the 3rd International Conference on Devices, Circuits and Systems (ICDCS), 2016, pp. 137–140.

J.-W. Yang and J. G. Fossum, “On the feasibility of nanoscale triple-gate CMOS transistors,” IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1159–1164, 2005., “Sentaurus TCAD User’s Manual,” in Synopsys Sentaurus Device, Synopsys, 2012.

D. B. M. Klaassen, “A unified mobility model for device simulation-I. Model equations and concentration dependence,” Solid. State. Electron., vol. 35, no. 7, pp. 953–959, 1992.

J. Del Alamo, S. Swirhun, and R. M. Swanson, “Simultaneous measurement of hole lifetime, hole mobility and bandgap narrowing in heavily doped n-type silicon,” in Proceedigns of the 1985 International Electron Devices Meeting, 1985, vol. 31, pp. 290–293.

W. Shockley and W. T. Read Jr, “Statistics of the recombinations of holes and electrons,” Phys. Rev., vol. 87, no. 5, p. 835, 1952.

S. Saha, “MOSFET test structures for two-dimensional device simulation,” Solid. State. Electron., vol. 38, no. 1, pp. 69–73, 1995.

N. Aggarwal, I. Gupta, K. Sikka, and R. Chaujar, “TCAD Linearity Performance Evaluation of Gate Workfunction Engineering in Surrounding Gate Silicon Nanowire MOSFET,” Nanoscale, vol. 9, no. B, p. 10, 2012.

S. Kang, B. Choi, and B. Kim, “Linearity analysis of CMOS for RF application,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 3, pp. 972–977, 2003.


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