### COMPARATIVE EVALUATION OF QUASI-DELAY-INSENSITIVE ASYNCHRONOUS ADDERS CORRESPONDING TO RETURN-TO-ZERO AND RETURN-TO-ONE HANDSHAKING

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ITRS design report. Available: http://www.itrs2.net

S. Kundu and A. Sreedhar, Nanoscale CMOS VLSI Circuits: Design for Manufacturability, McGrawHill, New York, USA, 2010.

A.J. Martin, S.M. Burns, T.K. Lee, D. Borkovic and P.J. Hazewindus, “The first asynchronous microprocessor: the test results,” ACM SIGARCH Computer Architecture News, vol. 17, pp. 95-98, 1989.

A.J. Martin and M. Nystrom, “Asynchronous techniques for system-on-chip design,” Proceedings of the IEEE, vol. 94, pp. 1089-1120, 2006.

C.H. Van Kees Berkel, M.B. Josephs and S.M. Nowick, “Scanning the technology applications of asynchronous circuits”, Proceedings of the IEEE, vol. 87, pp. 223-233, 1999.

S.B. Furber, D.A. Edwards and J.D. Garside, “AMULET3: a 100 MIPS asynchronous embedded processor,” In Proceedings of the International Conference on Computer Design, pp. 329-334, 2000.

L. Necchi, L. Lavagno, D. Pandini and L. Vanzago, “An ultra-low energy asynchronous processor for wireless sensor networks,” In Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems, 2006, pp. 1-8.

B.Z. Tang and F. Lane, “Low power QDI asynchronous FFT,” In Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016, pp. 87-88.

W. Jiang, D. Bertozzi, G. Miorandi, S.M. Nowick, W. Burleson and G. Sadowski, “An asynchronous NoC router in a 14nm FinFET library: comparison to an industrial synchronous counterpart,” In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 2017, pp. 732-733.

N.C. Paver, P. Day, C. Farnsworth, D.L. Jackson, W.A. Lien and J. Liu, “A low-power, low noise, configurable self-timed DSP”, In Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 32-42, 1998.

A.J. Martin and M. Nystrom, “Asynchronous techniques for noise tolerant nanoelectronics,” Technical Report Situs-TR-04-01, Situs Logic, Pasadena, CA, USA, 2004.

G.F. Bouesse, G. Sicard, A. Baixas and M. Renaudin, “Quasi delay insensitive asynchronous circuits for low EMI”, In Proceedings of the 4th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2004, pp. 27-31.

K.J. Kulikowski, V. Venkataraman, Z. Wang, A. Taubin and M. Karpovsky, “Asynchronous balanced gates tolerant to interconnect variability”, In Proceedings of the IEEE International Symposium on Circuits and Systems, 2008, pp. 3190-3193.

I.J. Chang, S.P. Park and K. Roy, “Exploring asynchronous design techniques for process-tolerant and energy-efficient subthreshold operation”, IEEE Journal of Solid-State Circuits, vol. 45, pp. 401-410, 2010.

I. David, R. Ginosar and M. Yoeli, “Self-timed is self-checking”, Journal of Electronic Testing: Theory and Applications, vol. 6, pp. 219-228, 1995.

L.A. Plana, P.A. Riocreux, W.J. Bainbridge, A. Bardsley, S. Temple, J.D. Garside, Z.C. Yu, “SPA – a secure Amulet core for smartcard applications,” Microprocessors and Microsystems, vol. 27, pp. 431446, 2003.

D. Sokolov, J. Murphy, A. Bystrov and A. Yakovlev, “Design and analysis of dual-rail circuits for security applications”, IEEE Transactions on Computers, vol. 54, pp. 449-460, 2005.

F. Burns, A. Bystrov, A. Koelmans and A. Yakovlev, “Design and security evaluation of balanced 1-of-n circuits,” IET Computers and Digital Techniques, vol. 6, pp. 125-135, 2012.

W. Cilio, M. Linder, C. Porter, J. Di, D.R. Thompson and S.C. Smith, “Mitigating power- and timingbased side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic,” Microelectronics Journal, vol. 44, pp. 258-269, 2013.

J. Sparsø and S. Furber (Eds.), Principles of Asynchronous Circuit Design: A Systems Perspective, Kluwer Academic Publishers, 2001.

M.T. Moreira and N.L.V. Calazans, “Quasi-delay-insensitive return-to-one design,” In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition PhD Forum, 2014, pp. 1-2.

M.T. Moreira, J.J.H. Pontes and N.L.V. Calazans, “Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design,” In Proceedings of the 15th International Symposium on Quality Electronic Design, 2014, pp. 692-699.

R.A. Guazzelli, M.T. Moreira and N.L.V. Calazans, “A comparison of asynchronous QDI templates using static logic,” In Proceedings of the 8th IEEE Latin American Symposium on Circuits and Systems, 2017, pp. 1-4.

A.J. Martin, “The limitation to delay-insensitivity in asynchronous circuits,” In Proceedings of the 6th MIT Conference on Advanced Research in VLSI, 1990, pp. 263-278.

P. Balasubramanian, C. Dang, “A comparison of quasi-delay-insensitive asynchronous adder designs corresponding to return-to-zero and return-to-one handshaking,” In Proceedings of the 60th IEEE International Midwest Symposium on Circuits and Systems, 2017, pp. 1192-1195.

T. Verhoeff, “Delay-insensitive codes – an overview”, Distributed Computing, vol. 3, pp. 1-8, 1988.

B. Bose, “On unordered codes”, IEEE Transactions on Computers, vol. 40, pp. 1-8, 1988.

P. Balasubramanian, “Comments on “Dual-rail asynchronous logic multi-level implementation”,” Integration, the VLSI Journal, vol. 52, pp. 34-40, 2016.

C.L. Seitz, “System Timing”, in Introduction to VLSI Systems, C. Mead and L. Conway (Editors), pp. 218-262, Addison-Wesley, Reading, Massachusetts, USA, 1980.

P. Balasubramanian and D.A. Edwards, “Efficient realization of strongly indicating function blocks”, In Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008, pp. 429-432.

P. Balasubramanian and D.A. Edwards, “A new design technique for weakly indicating function blocks”, In Proceedings of the 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008, pp. 116-121.

C. Brej, “Early output logic and anti-tokens,” PhD thesis, School of Computer Science, The University of Manchester, 2006.

P. Balasubramanian, “A robust asynchronous early output full adder,” WSEAS Transactions on Circuits and Systems, vol. 10, pp. 221-230, 2011.

C. Jeong and S.M. Nowick, “Block-level relaxation for timing-robust asynchronous circuits based on eager evaluation”, In Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008, pp. 95-104.

P. Balasubramanian, K. Prasad and N.E. Mastorakis, “Robust asynchronous implementation of Boolean functions on the basis of duality,” In Proceedings of the 14th WSEAS International Conference on Circuits, 2010, pp. 37-43.

P. Balasubramanian, R. Arisaka and H.R. Arabnia, “RB_DSOP: a rule based disjoint sum of products synthesis method”, In Proceedings of the 12th International Conference on Computer Design, 2012, pp. 39-43.

P. Balasubramanian and D.A. Edwards, “Self-timed realization of combinational logic”, In Proceedings of the 19th International Workshop on Logic and Synthesis, 2010, pp. 55-62.

P. Balasubramanian, “Self-timed logic and the design of self-timed adders”, PhD thesis, School of Computer Science, The University of Manchester, 2010.

P. Balasubramanian and N.E. Mastorakis, “A set theory based method to derive network reliability expressions of complex system topologies,” In Proceedings of the Applied Computing Conference, 2010, pp. 108-114.

J. Cortadella, A. Kondratyev, L. Lavagno and C. Sotiriou, “Coping with the variability of combinational logic delays,” In Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004, pp. 505-508.

V.I. Varshavsky (Ed.), Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems, Chapter 4: Aperiodic Circuits, pp. 77-85, (Translated from the Russian by A.V. Yakovlev), Kluwer Academic Publishers, 1990.

P. Balasubramanian and K. Prasad, “Early output hybrid input encoded asynchronous full adder and relative-timed ripple carry adder,” In Proceedings of the 14th International Conference on Embedded Systems, Cyber-physical Systems, and Applications, 2016, pp. 62-65.

P. Balasubramanian and S. Yamashita, “Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders,” SpringerPlus, vol. 5, pages 26, 2016.

P. Balasubramanian and K. Prasad, “Latency optimized asynchronous early output ripple carry adder based on delay-insensitive dual-rail data encoding,” International Journal of Circuits, Systems and Signal Processing, vol. 11, pp. 65-74, 2017.

K.S. Stevens, R. Ginosar and S. Rotem, “Relative timing,” IEEE Transactions on VLSI Systems, vol. 11, pp. 129-140, 2003.

D. Bhadra and K.S. Stevens, “Design of a low power, relative timing based asynchronous MSP430 processor,” In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp. 794-799, 2017.

M.M. Mano and M.D. Ciletti, Digital Design, 4th edition, Prentice-Hall, New Jersey, USA, 2007.

Synopsys Digital Standard Cell Library SAED_EDK32/28_CORE Databook, Revision 1.0.0, 2012.

N.P. Singh, “A design methodology for self-timed systems,” MSc dissertation, Massachusetts Institute of Technology, USA, 1981.

W.B. Toms, “Synthesis of quasi-delay-insensitive datapath circuits”, PhD thesis, School of Computer Science, The University of Manchester, UK, 2006.

P. Balasubramanian, “A latency optimized biased implementation style weak-indication self-timed full adder,” Facta Universitatis, Series: Electronics and Energetics, vol. 28, pp. 657-671, 2015.

J. Sparsø and J. Staunstrup, “Delay-insensitive multi-ring structures”, Integration, the VLSI Journal, vol. 15, pp. 313-340, 1993.

B. Folco, V. Bregier, L. Fesquet and M. Renaudin, “Technology mapping for area optimized quasi delay insensitive circuits”, In Proceedings of the IFIP 13th International Conference on Very Large Scale Integration of System-on-Chip, 2005, pp. 146-151.

W.B. Toms and D.A. Edwards, “A complete synthesis method for block-level relaxation in self-timed datapaths,” In Proceedings of the 10th International Conference on Application of Concurrency to System Design, 2010, pp. 24-34.

P. Balasubramanian and D.A. Edwards, “A delay efficient robust self-timed full adder”, In Proceedings of the IEEE 3rd International Design and Test Workshop, 2008, pp. 129-134.

P. Balasubramanian, D.A. Edwards and W.B. Toms, “Self-timed section-carry based carry lookahead adders and the concept of alias logic,” Journal of Circuits, Systems, and Computers, vol. 22, pp. 1350028-1–1350028-24, 2013.

P. Balasubramanian, D. Dhivyaa, J.P. Jayakirthika, P. Kaviyarasi and K. Prasad, “Low power self-timed carry lookahead adders,” In Proceedings of the 56th IEEE International Midwest Symposium on Circuits and Systems, 2013, pp. 457-460.

P. Balasubramanian, “Asynchronous carry select adders,” Engineering Science and Technology, an International Journal, vol. 20, pp. 1066-1074, 2017.

P. Balasubramanian and N.E. Mastorakis, “QDI decomposed DIMS method featuring homogeneous/ heterogeneous data encoding”, In Proceedings of the International Conference on Computers, Digital Communications and Computing, 2011, pp. 93-101.

P. Balasubramanian and D.A. Edwards, “Power, delay and area efficient self-timed multiplexer and demultiplexer designs,” In Proceedings of the 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2009, pp. 173-178, 2009.

N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd edition, Addison-Wesley Publishing Company, Massachusetts, USA, 1993.

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