Vladimir Milovanović, Horst Zimmermann

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A novel fully complementary and fully differential asynchronous CMOS comparator architecture, that consists of a two-stage preamplifier cas- caded with a latch, achieves a sub-100 ps propagation delay for a 50mVpp and higher input signal amplitudes under 1.1V supply and 2.1mWpower consumption. The proposed voltage comparator topology features two differential pairs of inputs (four in total) thus increasing signal-to-noise ratio (SNR) and noise immunity through rejection of the coupled noise components, reduced even-order harmonic distortion, and doubled output voltage swing. In addition to that, the comparator is truly self-biased via negative feedback loop thereby eliminating the need for a voltage reference and suppressing the influence of process, supply voltage and ambient temperature variations. The described analog comparator prototype occupies 0.001mm2 in a purely digital 40 nm LP (low-power) CMOS process technology. All the above mentioned merits make it highly attractive for use as a building block in implementation of the leading-edge system-on-chip (SoC) data transceivers and data converters.

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T. Sepke et al., “Comparator-based switched-capacitor circuits for scaled CMOS technologies,” in ISSCC Dig. Tech.Papers, Feb. 2006, pp. 812–821.

D. Schinkel et al., “A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time,” in ISSCC Dig. Tech.Pap., Feb. 2007, pp. 314–315.

V. Srinivasan et al., “A 20mW 61 dB SNDR (60MHz BW) 1 b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45 nm CMOS,” in ISSCC Dig. Tech.Papers, Feb. 2012, pp. 812–821.

C.-Y. Yang and S.-I. Liu, “A one-wire approach for skew-compensating clock distribution based on bidirectional techniques,” IEEE Journal of Solid-State Circuits, vol. 36, no. 2, pp. 266–272, Feb. 2001.

M.-C. Huang and S.-I. Liu, “A fully differential comparator-based switched-capacitor __ modulator,” IEEE Transactions on Circuits and Systems II: Express

Briefs, vol. 56, no. 5, pp. 369–373, May 2009.

M. Bazes, “Two novel fully complementary self-biased CMOS differential amplifiers,” IEEE J. of Solid-State Circuits, vol. 26, no. 2, pp. 165–168, Feb. 1991.

B. J. McCarroll et al., “A high-speed CMOS comparator for use in an ADC,” IEEE Journal of Solid-State Circuits, vol. 23, no. 1, pp. 159–165, Feb. 1988.


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