### BINARY TO RNS ENCODER FOR THE MODULI SET {2n−1,2n ,2n+1} WITH EMBEDDED DIMINISHED-1 CHANNEL FOR DSP APPLICATION

**DOI Number**

**First page**

**Last page**

#### Abstract

the moduli set {2n − 1,2n,2n + 1} with embedded modulo 2n + 1 channel in the diminished-1 representation, which can be used instead of the standard modulo 2n+1 channel, is presented. We consider the binary numbers with dynamic range of proposed moduli set which is 23n−2n. Within this dynamic range, 3n-bit binary number is partitioned into three n-bit parts and converted to residue numbers. The proposed architecture based on moduli set {2n−1,2n ,2n+1} with embedded diminished-1 encoded channel have been mapped on Xilinx FPGA chip. The proposed architecture can be utilized in conjunction with any fast binary adder without requiring any extra hardware.

#### Keywords

#### Full Text:

PDF#### References

H. L. Garner, “The residue number system,” IRE Trans. Electronic Computer, vol. EC-8, no. Issue 2, pp. 140–147, June 1959.

N. Szabo and R. I. Tanaka, Residue Arithmetic and its Application to Computer Technology. New York: McGraw-Hill, 1967.

E. Gholami, R. Farshidi,M. Hosseinzadeh, and K. Navi, “High speed residue number system comparison for the moduli set {2n−1,2n ,2n+1}.”

R. Chaves and L. Sousa, “RDSP: a RISC DSP based on residue number system,” in Digital System Design, 2003. Proceedings. Euromicro Symposium on, Belek- Antalya, Turkey, Sept. 1–6, 2003, pp. 128–135.

N. Stamenkovi´c, Digital filter implementation using RNS-binary arithmetic, monographies ed. LAP Lambert Academic Publishing, 2014.

D. ˇZivaljevi´c, N. Stamenkovi´c, and V. Stojanovi´c, “Digital filter implementation based on the RNS with diminished-1 encoded channel,” in Telecommunications and Signal Processing (TSP), 2012 35th International Conference on, Prague, Czech Republic, July 3–4, 2012, pp. 662–666.

N. Stamenkovi´c, D. ˇZivaljevi´c, and V. Stojanovi´c, “The use of residue number system in the design of the optimal all-pole IIR digital filters,” in Telecommunications and Signal Processing (TSP), 2013 36th International Conference on, Rome, Italy, July 2–4, 2013, pp. 722–726.

D. ˇZivaljevi´c, N. Stamenkovi´c, and V. Stojanovi´c, “FIR filter implementation based on the RNS with diminished-1 encoded channel,” International Journal of Advances

in Telecommunications, Electrotechnics, Signals and Systems, vol. 2, no. 2, pp. 56–62, 2013.

W. K. Jenkins and B. Leon, “The use of residue number systems in the design of finite impulse response digital filters,” IEEE Trans. on Circuits and Systems, vol. CAS-24, no. 4, pp. 191–201, Apr. 1977.

K.-W. Kim and W.-J. Lee, “An efficient parallel systolic array for AB2 over GF(2n),” IEICE Electronics Express, vol. 10, no. 20, pp. 1–6, 2013.

R. Capocelli and R. Giancarlo, “Efficient vlsi networks for converting an integer from binary system to residue number system and vice versa,” Circuits and Systems, IEEE

Transactions on, vol. 35, no. 11, pp. 1425–1430, 1988.

J. Low and C.-H. Chang, “A new approach to the design of efficient residue generators for arbitrary moduli,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 60, no. 9, pp. 2366–2374, Sept. 2013.

F. Pourbigharaz and H. M. Yassine, “Modulo-free architecture for binary to residue transformation with respect to {2m−1,2m ,2m+1} moduli set,” in Circuits and Systems,

ISCAS ’94., 1994 IEEE International Symposium on, vol. 2, 1994, pp. 317–320 vol.2.

M.-H. Sheu, S.-H. Lin, Y.-T. Chen, and Y.-C. Chang, “High-speed and reduced-area RNS forward converter based on (2n−1,2n ,2n+1) moduli set,” in Circuits and Systems,

Proceedings. The 2004 IEEE Asia-Pacific Conference on, vol. 2, 2004, pp. 821–824.

L. M. Leibowitz, “A simplified binary arithmetic for the Fermat number transform,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-24, no. 5, pp. 356–359, Oct. 1976.

H. Vergos and C. Efstathiou, “A unifying approach for weighted and diminished-1 modulo 2n+1 addition,” Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 55, no. 10, pp. 1041–1045, Oct. 2008.

C. Efstathiou, I. Voyiatzis, and N. Sklavos, “On the modulo 2n +1 multiplication for diminished-1 operands,” in Signals, Circuits and Systems, 2008. SCS 2008. 2nd International Conference on, Monastir, Tunisia, Nov. 7–9, 2008, pp. 1–5.

E. Vassalos, D. Bakalis, and H. Vergos, “Reverse converters for RNSs with diminished-one encoded channels,” in EUROCON, 2013 IEEE, July 1–4, 2013, pp. 1798–1805.

B. Vinnakota and V. V. B. Rao, “Fast conversion techniques for binary-residue number systems,” IEEE Trans. On Circuits And Systems-I: Fundamental Theories And Applications, vol. 41, no. 12, pp. 927–929, Dec. 1994.

S. J. Piestrak, “Design of residue generators and multioperand modular adders using carry-save adders,” IEEE Transactions on Computers, vol. 423, no. 1, pp. 68–77, Jan.

E. Vassalos, D. Bakalis, and H. Vergos, “On the design of modulo 2n±1 subtractors and adders/subtractors,” Circuits Syst Signal Process, vol. 30, no. 6, pp. 1445–1461, 2011.

R. Chaves and L. Sousa, “{2n +1,2n+k ,2n −1}: A new RNS moduli set extension,” in Proceedings of the EUROMICRO Systems on Digital System Design (DSD’04), Remes, France, Aug. 31/Sept. 03, 2004, pp. 210–217.

C. Efstathiou, H. Vergos, and D. Nikolos, “Fast parallel-prefix modulo 2n+1 adders,” Computers, IEEE Transactions on, vol. 53, no. 9, pp. 1211–1216, Sept. 2004.

S.V.Padmajarani and M.Muralidhar, “A new approach to implement parallel prefix adders in an FPGA,” International Journal of Engineering Research and Applications (IJERA), vol. 2, no. 4, pp. 1524–1528, July-August 2012. [Online]. Available: www.ijera.com

### Refbacks

- There are currently no refbacks.

ISSN: 0353-3670 (Print)

ISSN: 2217-5997 (Online)

COBISS.SR-ID 12826626