Sandeep Kumar Dash, Satya Narayan Mishra, Nirmal Kumar Rout

DOI Number
First page
Last page


In recent years researchers have been  focusing on the design of low power and small size oscillator for emerging areas of interest such as the internet of things (IoT) and biomedical applications. In this paper a new delay block for ring oscillator is proposed using CMOS inverter cascaded with inverted current starved inverter (CICSI). The designed delay block provides approximately 50% more delay with a smaller number of transistors than the conventionally designed circuits. Furthermore, a ring oscillator and a non-overlapping clock (NOC) generator are designed using it. The designed circuits can be used in switched capacitor (SC) circuits, analog mixed signal circuits to meet the need for low frequency portable biomedical applications. The designed circuits are simulated on Generic 90nm 1.2V Process Design Kit (GPDK90) using Cadence Virtuoso Design Environment. The simulation result shows the delay of the CICSI delay block is 592ps. The ring oscillator using 101 stages of delay block is designed and it is shown that it operates at a frequency of  17MHz with a power consumption of 420µW.


CMOS inverter, Inverted current starved inverter, NOC

Full Text:



P. E. Allen, E. Sanchez-Sinencio, Switched Capacitor Circuits, Van Nostrand Rienhold, 1984.

Roubik Gregorian, Gabor C. Temes, Analog MOS & Integrated Circuits for signal processing, John WileySons, 1986.

David A. Johns, Ken Martin, Analog Integrated Circuit Design, John Wiley & Sons, 1997.

B. Razavi, “The Ring Oscillator [A Circuit for All Seasons]”, in IEEE Solid-State Circuits Magazine, vol. 11, no. 4, pp. 10-81, Fall 2019.

G. Jovanovic, M. Stojcev, “A Method for Improvement Stability of a CMOS Voltage Controlled Ring Oscillators”, In Proceedings of the ICEST2007, Ohrid, June 2007, vol. 2, pp. 715–718.

R. S. S. M. R. Krishna, G. L. Madhumati and A. K. Mal, “Design of substantial delay block using voltage scaled CMOS inverter and transmission gate blend”, In Proceedings of the 2016 International Conference on Microelectronics, Computing and Communications (MicroCom), Durgapur, 2016, pp. 1–6,

Meng-LiehSheu, Ta-Wei Lin, Wei-Hung Hsu, “Wide frequency range voltage controlled ring oscillator based on transmission gates”, ISCAS 2005, vol. 3, pp. 2731–2734, May 2005.

T.Jiang,J.Yin,P.Mak and R.P.C.Martins, “A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 2, pp. 157-161, Feb. 2019.

F. Pepe and P. Andreani, “An Accurate Analysis of Phase Noise in CMOS Ring Oscillators”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 8, pp. 1292–1296, Aug. 2019.

B.J. V. T. Ferreira and C. Galup-Montoro, “Ultra-low-voltage CMOS ring oscillators”, Electronics Letters, vol. 55, no. 9, pp. 523–525, 2 5 2019.

B. S. Salem, H. Zandevakili, A. Mahani and M. Saneei, “Fault-tolerant delay cell for ring oscillator application in 65 nm CMOS technology”, IET Circuits, Devices & Systems, vol. 12, no. 3, pp. 233–241, 2018.

B.X. Yu, Y. Fang and Z. Shi, “2.5 mW 2.73 GHz non-overlapping multi-phase clock generator with duty-cycle correction in 0.13 µm CMOS”, Electronics Letters, vol. 52, no. 14, pp. 1261–1262, 2016.

P. Angelov, M. Nielsen-Lönn and A. Alvandpour, “Ring-oscillator-based timing generator for ultralow-power applications”, In Proceedings of the 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), Linkoping, pp. 1–4, 2017.

B.Nowacki, N. Paulino and J. Goes, “A simple 1 GHz non-overlapping two-phase clock generators for SC circuits”, In Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013, Gdynia, pp. 174–178.

B.L. Minatiet al., “Current-Starved Cross-Coupled CMOS Inverter Rings as Versatile Generators of Chaotic and Neural-Like Dynamics Over Multiple Frequency Decades”, IEEE Access, vol. 7, pp. 54638–54657, 2019.

B.C. Q. Liu, Y. Cao and C. H. Chang, “ACRO-PUF: A Low-power, Reliable and Aging-Resilient Current Starved Inverter-Based Ring Oscillator Physical Unclonable Function”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 12, pp. 3138–3149, Dec. 2017.

A.K. Mal, R. Thodani,”Non overlapping clock (NOC) generator for low frequency switched capacitor circuits”, In Proceedings of the students Technology symposium 2011 IEEE, pp. 226–231.

A. K. Mal and R. Todani, “Non Overlapping Clock generator for switched capacitor circuits in Bio-Medical applications”, In Proceedings of the 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies, Thuckafay, 2011, pp. 238–243.

S.M. Kang, Y. Lebebici, CMOS Digital Integrated Circuits,Analysis and Design, McGraw-Hili Publishing Company LImIted, 2003.

N. N. Singh and P. P. Bansod, “Switched-capacitor filter design for ECG application using 180nm CMOS technology”, IN Proceedings of the 2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE), Bhopal, 2017, pp. 439–443.

A. Karimi-Bidhendi et al., “CMOS Ultralow Power Brain Signal Acquisition Front-Ends: Design and Human Testing” IEEE Transactions on Biomedical Circuits and Systems, vol. 11, no. 5, pp. 1111–1122, 2017.


  • There are currently no refbacks.

ISSN: 0353-3670 (Print)

ISSN: 2217-5997 (Online)

COBISS.SR-ID 12826626