PLANAR CMOS AND MULTIGATE TRANSISTORS BASED WIDE-BAND OTA BUFFER AMPLIFIERS FOR HEAVY RESISTANCE LOAD

Remya Jayachandran, Dhanaraj Kakkanattu Jagalchandran, Perinkolam Chidambaram Subramaniam

DOI Number
https://doi.org/10.2298/FUEE2201013J
First page
013
Last page
028

Abstract


Analog buffer amplifier configurations capable of driving heavy resistive load using different operational transconductance amplifier (OTA) are presented in this paper. The OTA CMOS buffer configurations are designed using 0.18 µm SCL technology library in Cadence Virtuoso tool and multigate transistor OTA buffer in TCAD Sentaurus tool. CMOS OTA buffer configuration using simple OTA outperform the OTA buffer circuits using other OTAs in terms of power dissipation and stability. Measured results show that the OTA buffer circuit works well for resistive load below 100 Ω. The gain tuning of up to 5 V/V is achieved with RL equal to 50 Ω, output swing of 1 V. OTA buffer configuration implemented using multigate transistor with resistive load below 1 kΩ exhibits a bandwidth around 5 GHz and tunable gain up to 5 V/V.

Keywords

OTA, buffer amplifier, resistive load, multigate transistor

Full Text:

PDF

References


R. Jayachandran, K. J. Dhanaraj and P. C. Subramaniam, "Hardware realization and testing of multistage OTA buffer amplifier for heavy resistive load", In Proceedings of 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 550–554.

R. Jayachandran, P. C. Subramaniam and K. J. Dhanaraj, "A novel tunable gain CMOS buffer amplifier for large resistive loads", Integration, vol. 77, pp. 1–12, March 2021.

Y. Ha, M. Li and A. Q. Liu, "A new CMOS buffer amplifier design used in low voltage MEMS interface circuits", Analog Integ. Circuits Signal Process., vol. 27, no. 1–2, pp. 7–17, Apr. 2001.

K. Moolpho and J. Ngarmnil, "Low voltage high-performance class-AB FGMOS buffer", in Proceedings of IEEE Asia Pacific Conference on Circuits and Systems, 2006, pp. 1779–1782.

C. Mohan and P. M. Furth, "A 16-Ohm audio amplifier with 93.8-mW peak load power and 1.43-mW quiescent power consumption", IEEE Trans. Circuits and Systems II: Express Briefs, vol. 59, no. 3, pp. 133–137, March 2012.

X. Qiu, D. Chen and Z. Wang, "Response of ring oscillator to periodic interference on the power supply", AEU-Int. J. Electron. Commun., vol. 82, pp. 383–390, Dec. 2017.

J. Remya et. al., "High performance reconfigurable FET for a simple variable gain buffer amplifier design", Int. J. Electron., Apr. 2021. (published online)

R. Jayachandran, R. S. Komaragiri and P. C. Subramaniam, "Reconfigurable circuits based on Single Gate Reconfigurable Field-Effect Transistors", In Proceedings of 6th IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), 2020, pp.1–5.

V. Khadem et. al., "An analytical approach to model capacitance and resistance of capped carbon nanotube single electron transistor", AEU-Int. J. Electron. Commun., vol. 90, pp. 97–102, June 2018.

Y.-M. Lin et. al., "High-performance carbon nanotube field-effect transistor with tunable polarities", IEEE Trans. Nanotechnol., vol. 4, no. 5, pp. 481–489, Sept. 2005.

G. Darbandy, M. Claus and M. Schröter, "High-performance reconfigurable Si nanowire field-effect transistor based on simplified device design", IEEE Trans. Nanotechnol., vol. 15, no. 2, pp. 289–294, March 2016.

A. Heinzig et. al., "Reconfigurable Silicon nanowire transistors", Nano Letters, vol. 12, no. 1, pp. 119–124, Nov. 2011.

W. M. Weber et. al., "Tuning the polarity of Si-nanowire transistors without the use of doping", in proceedings of 8th IEEE Conference on Nanotechnology, NANO’08, 2008, pp. 580–581.

F. Wessely, T. Krauss and U. Schwalke, "CMOS without doping: Multi-gate silicon-nanowire field-effect-transistors", IEEE J. Solid-State Circ., vol. 70, pp. 33–38, Apr. 2012.

D. Sacchetto, Y. Leblebici and G. De Micheli, "Ambipolar gate-controllable SiNW FETs for configurable logic circuits with improved expressive capability", IEEE Electron Device Lett., vol. 33, no. 2, pp. 143–145, Feb. 2012.

R. Ranjith et. al., "Two dimensional analytical model for a reconfigurable field effect transistor", Superlattice. Microstruct., vol. 114, pp. 62–74, Feb. 2018.

R. S. Assaad and J. Silva-Martinez, "The recycling folded cascode: A general enhancement of the folded cascode amplifier", IEEE J. of Solid-State Circ., vol. 44, no. 9, pp. 2535–2542, Sept. 2009.

A. S. Khade, V. Vyas and M. Sutaone, "Performance enhancement of advanced recycling folded cascode operational transconductance amplifier using an unbalanced biased input stage", Integration, vol. 69, pp. 242–250, Nov. 2019.

D. Binkley, B. Blalock and J. Rochelle, "Optimizing drain current, inversion level, and channel length in analog CMOS design", Analog Integ. Circuits Signal Process, vol. 47, no. 2, pp. 137–163, March 2006.


Refbacks

  • There are currently no refbacks.


ISSN: 0353-3670 (Print)

ISSN: 2217-5997 (Online)

COBISS.SR-ID 12826626