Debarshi Datta, Himadri Sekhar Dutta

DOI Number
First page
Last page


This paper presents a field-programmable gate array (FPGA)-based digital down converter (DDC) that can reduce the bandwidth from about 70 MHz to 182.292 kHz. The proposed DDC consists of a polyphase COordinate Rotation DIgital Computer (CORDIC) processor and a multirate filter. The advantage of polyphase CORDIC processor is to process with high sample rate input data and produces computational efficient noiseless baseband spectrum. The pipeline multirate filter works at a high clock speed. Moreover, the multirate filter generates a fractional sample rate factor using a cubic B-spline Farrow filter. The proposed DDC is coded with optimal hardware description language (HDL) and tested on Kintex-7 Xilinx FPGA as the target device. Experimental results indicate that the proposed design saves chip area, power consumption and operates at high speed without loss of any functionality. Additionally, the proposed design offers sufficient spurious-free dynamic range (SFDR) and produces less than 1 Hz frequency resolution at the output.


Digital down converter (DDC), COordinate Rotation DIgital Computer (CORDIC), Half-band (HB) filter, Field programmable gate array (FPGA), MATLAB

Full Text:



A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing, Third Edition. Prentice Hall, 2010.

W. Wolf, FPGA-Based System Design. Englewood Cliffs, NJ: Prentice- Hall, 2004.

L. L. Motta, B. A. Acurio, N. F. T. Aniceto and Luís Geraldo P. Meloni, "Design and implementation of a digital down/up conversion directly from/ to RF channels in HDL", Integration, vol. 68, pp. 30–37, Sept. 2019.

L. Guo, F. Tan, P. Zhan and H. Zeng, "Decomposing numerically controlled oscillator in parallel digital down conversion architecture", J. Circuits, Syst. Comput., vol. 26, no. 9, p. 1750126, Feb. 2017.

X. Liu, X. Yan, Z. Wang, and Q. Deng, "Design and FPGA implementation of a reconfigurable digital down converter for wideband applications", IEEE Trans. on VLSI systems, vol. 25, no. 12, Dec. 2017.

B. H. Tietche, O. Romain, and B. Denby, "A Practical FPGA-Based Architecture for Arbitrary-Ratio Sample Rate Conversion", J. Sign. Process. Syst., vol. 78, pp. 147–154, Feb. 2015.

V. Obradović, P. Okiljević, N. Kozić and D. Ivković, "Practical implementation of digital down conversion for wideband direction finder on FPGA", Sci. Tech. Rev., vol. 66, no. 4, pp. 40–46, Jan. 2016.

J. Thabet, R. Barrak, N. Kamoun, N. Khouja and A. Ghazel, "A reconfigurable Digital Down Converter architecture for multistandard GNSS receiver", In Proceedings of the 14th International Symposium on Communications and Information Technologies (ISCIT), Incheon, 2014, pp. 404–408.

A. Agarwal, L. Boppana and K. R. Kodali, "A factorization method for FPGA implementation of Sample Rate Converter for a multi-standard radio communications", In Proceedings of the 2013 Tencon - Spring, Sydney, NSW, 2013, pp. 530–534.

D. Datta, P. Mitra and H. S. Dutta, "FPGA implementation of high performance digital down converter for software defined radio", Microsyst. Technol., vol. 28, pp. 533–542, Aug. 2019.

J. E. Volder, "The CORDIC trigonometric computing technique", IRE Trans. Electron. Comput., vol. EC–8, pp. 330–334, Sept. 1959.

E. B. Hogenauer, "An economical class of digital filters for decimation and interpolation", IEEE Trans. Acoustic Speech, Signal Process, vol. ASSP-29, no. 2, pp.155–162, April 1981.

Q. Jing, Y. Li, and J. Tong, "Performance analysis of multi-rate signal processing digital filters on FPGA", EURASIP J. Wirel. Commun. Netw., p. 31, Feb. 2019.

U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, Springer, Third Edition, 2007.

P. P. Vaidyanathan and T. Q. Nguyen, "A “TRICK” for the Design of FIR Half-Band Filters", IEEE Trans. Circuits Syst., vol. CAS–34, no. 3, Mar. 1987.

A. N. Willson, "Desensitized Half-Band Filters", IEEE Trans. Circuits Syst.–I: Regul. Pap., vol. 57, no. 1, pp. 152-167, Jan. 2010.

MathWorks HDL Coder, Accessed 14 Aug. 2019.

R. Ratan, S. Sharma and A. K. Kohli, "Cubic Lagrange polynomial-based designing of efficient interpolators", Int. J. Electron. Lett., vol. 2, no. 1, pp. 8–16, Nov. 2013.

C. Farrow, "A continuously variable digital delay element", In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS88), 1998, pp. 2642–2645.

D. Datta, P. Mitra and H. S. Dutta, "Implementation of Fractional Sample Rate Digital Down Converter for Radio Receiver Applications", In Proceedings of the Devices for Integrated Circuit (DevIC), Kalyani, 2021, pp. 94–98.

R. Yates, "Fixed-Point Arithmetic: An Introduction" 2007. Available at:

S. Navid Shahrouzi and Darshika G. Perera, "HDL Code Optimizations: Impact on Hardware Implementations and CAD Tools", In Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), Canada, 2019, pp. 1–9.

Z. Zulfikar, "Novel area optimization in FPGA implementation using efficient vhdl code", Jurnal Rekayasa Elektrika, vol. 10, no. 2, pp. 61–66, Oct. 2012.


  • There are currently no refbacks.

ISSN: 0353-3670 (Print)

ISSN: 2217-5997 (Online)

COBISS.SR-ID 12826626