Biswajit Jena, Kumar Prasannajit Pradhan, Prasanna Kumar Sahu, Sidharth Dash, Guru Prasad Mishra, Sushanta Kumar Mohapatra

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Undoped cylindrical gate all around (GAA) MOSFET is a radical invention and a potential candidate to replace conventional MOSFET, as it introduces new direction for transistor scaling. In this work, the sensitivity of process parameters like channel length (Lg), channel thickness (tSi), and gate work function (φM) on various performance metrics of an undoped cylindrical GAA to nanowire MOSFET are systematically analyzed. The electrical characteristics such as on current (Ion), subthreshold leakage current (Ioff), threshold voltage (Vth) and similarly analog/RF performances like transconductance (gm), total gate capacitance (Cgg), and cut-off frequency (fT) are evaluated and studied with the variation of device design parameters. The discussion give direction towards low standby operating power (LSTP) devices as improvement in Ioff is approaching 90% in nanowire MOSFET. All the device performances of undoped GAA MOSFET are investigated through Sentaurus device simulator from Synopsis Inc.

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K. K. Young, “Short-channel effect in fully depleted SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399–402, 1989.

S. Bangsaruntip, G. M. Cohen, A. Majumdar, and J. W. Sleight, “Universality of short-channel effects in undoped-body silicon nanowire MOSFETs,” IEEE Electron Device Lett., vol. 31, no. 9, pp. 903–905, 2010.

T. Skotnicki, J. A. Hutchby, T. J. King, H. S. P. Wong, and F. Boeuf, “The end of CMOS scaling: Toward the introduction of new materials and structural changes to improve MOSFET performance,” IEEE Circuits Devices Mag., vol. 21, no. 1, pp. 16–26, 2005.

J. P. Colinge, “Multiple-gate SOI MOSFETs,” Solid. State. Electron., vol. 48, no. 6, pp. 897–905, 2004.

L. Chang, Y. C. Y. Choi, D. Ha, P. Ranade, S. X. S. Xiong, J. Bokor, C. Hu, and T. J. King, “Extremely scaled silicon nano-CMOS devices,” Proc. IEEE, vol. 91, no. 11, pp. 1860–1873, 2003.

V. M. Srivastava, K. S. Yadav, and G. Singh, “Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch,” Microelectronics J., vol. 42, no. 3, pp. 527–534, 2011.

J. Colinge, “From gate-all-around to nanowire MOSFETs,” in Semiconductor Conference, 2007. CAS 2007. International, 2007, vol. 1, pp. 11–17.

T.-K. Chiang and J. J. Liou, “An analytical subthreshold current/swing model for junctionless cylindrical nanowire FETs (JLCNFETs),” Facta Univ. Electron. Energ., vol. 26, no. 3, pp. 157–173, 2013.

S. K. Gupta and S. Baishya, “Modeling of cylindrical surrounding gate MOSFETs including the fringing field effects,” J. Semicond., vol. 34, no. 7, pp. 1–6, 2013.

M. R. Kumar, S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “A simple analytical center potential model for cylindrical gate all around (CGAA) MOSFET,” J. Electron Devices, vol. 19, pp. 1648–1653, 2014.

H. Abd-Elhamid, B. Iñiguez, D. Jiménez, J. Roig, J. Pallarès, and L. F. Marsal, “Two-dimensional analytical threshold voltage roll-off and subthreshold swing models for undoped cylindrical gate all around MOSFET,” Solid. State. Electron., vol. 50, no. 5, pp. 805–812, 2006.

R. Gautam, M. Saxena, R. S. Gupta, and M. Gupta, “Gate all around MOSFET with vacuum gate dielectric for improved hot carrier reliability and RF performance,” Electron Devices, IEEE Trans., vol. 60, no. 6, pp. 1820–1827, 2013.

A. Cerdeira, M. Estrada, J. Alvarado, I. Garduño, E. Contreras, J. Tinoco, B. Iniguez, V. Kilchytska, and D. Flandre, “Review on double-gate MOSFETs and FinFETs modeling,” Facta Univ. Electron. Energ., vol. 26, no. 3, pp. 197–213, 2013.

Y. Pratap, P. Ghosh, S. Haldar, R. S. Gupta, and M. Gupta, “An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering,” Microelectronics J., vol. 45, no. 4, pp. 408–415, 2014.

T. K. Chiang, “A compact model for threshold voltage of surrounding-gate MOSFETs with localized interface trapped charges,” IEEE Trans. Electron Devices, vol. 58, no. 2, pp. 567–571, 2011.

L. Zhang, C. Ma, J. He, X. Lin, and M. Chan, “Analytical solution of subthreshold channel potential of gate underlap cylindrical gate-all-around MOSFET,” Solid. State. Electron., vol. 54, no. 8, pp. 806–808, 2010.

D. Sharma and S. K. Vishvakarma, “Precise analytical model for short channel Cylindrical Gate (CylG) Gate-All-Around (GAA) MOSFET,” Solid. State. Electron., vol. 86, pp. 68–74, 2013.

I. Ferain, C. A. Colinge, and J. Colinge, “Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors,” Nature, vol. 479, pp. 310–316, 2011.

K. P. Pradhan, S. K. Mohapatra, P. K. Sahu, and D. K. Behera, “Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET,” Microelectronics J., vol. 45, no. 2, pp. 144–151, 2014.

S. K. Mohapatra, K. P. Pradhan, L. Artola, and P. K. Sahu, “Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET,” Mater. Sci. Semicond. Process., vol. 31, no. 0, pp. 455–462, 2015.

S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Resolving the bias point for wide range of temperature applications in high-k/metal gate nanoscale DG-MOSFET,” Facta Univ. Ser. Electron. Energ., vol. 27, no. 4, pp. 613–619, 2014., “Sentaurus TCAD User’s Manual,” in Synopsys Sentaurus Device, pp. 191–403.

S. M. Sze, Physics of Semiconductor Devices, Third Edit. John Wiley and Sons Inc., 2009.

Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor. Oxford Univ. Press, 2011.

A. Tsormpatzoglou, D. H. Tassis, C. A. Dimitriadis, G. Ghibaudo, G. Pananakakis, and R. Clerc, “A compact drain current model of short-channel cylindrical gate-all-around MOSFETs,” Semicond. Sci. Technol., vol. 24, no. 7, p. 75017, 2009.


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