Sedaghat, Reza, Electrical and Computer Engineering, Ryerson University Toronto, Canada, Canada
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Vol 27, No 2 (2014) - INVITED PAPERS
EXECUTION TIME – AREA TRADEOFF IN GAUSING RESIDUAL LOAD DECODER: INTEGRATED EXPLORATION OF CHAINING BASED SCHEDULE AND ALLOCATION IN HLS FOR HARDWARE ACCELERATORS
Abstract PDF -
Vol 27, No 3 (2014) - INVITED PAPERS
RAPID EXPLORATION OF COST-PERFORMANCE TRADEOFFS USING DOMINANCE EFFECT DURING DESIGN OF HARDWARE ACCELERATORS
Abstract PDF
ISSN: 0353-3670 (Print)
ISSN: 2217-5997 (Online)
COBISS.SR-ID 12826626