### PERFORMANCE ANALYSIS OF FINFET BASED INVERTER, NAND AND NOR CIRCUITS AT 10 NM ,7 NM AND 5 NM NODE TECHNOLOGIES

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#### Abstract

Advancement in the semiconductor industry has transformed modern society. A miniaturization of a silicon transistor is continuing following Moore’s empirical law. The planar metal-oxide semiconductor field effect transistor (MOSFET) structure has reached its limit in terms of technological node reduction. To ensure the continuation of CMOS scaling and to overcome the Short Channel Effect (SCE) issues, a new MOS structure known as Fin field-effect transistor (FinFET) has been introduced and has led to significant performance enhancements.

This paper presents a comparative study of CMOS gates designed with FinFET 10 nm, 7 nm and 5 nm technology nodes. Electrical parameters like the maximum switching current I_{ON}, the leakage current I_{OFF}, and the performance ratio I_{ON}/I_{OFF} for N and P FinFET with different nodes are presented in this simulation.

_{d}=1.4 ps for CMOS NOT gate and t

_{d}=1 ps for CMOS NOR gate to improve Integrated Circuits IC.

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B. Yu, L. Chang and S. Ahmed, "FinFET scaling to 10 nm gate length". In Proceedings of the IEEE Digest. International Electron Devices Meeting", 2002, pp. 251-254.

A. Lazzaz, K. Bousbahi and M. Ghamnia, "Modeling and Simulation of DG SOI N FinFET 10 nm using Hafnium Oxide", In Proceedings of the 21st IEEE International Conference on Nanotechnology (NANO), 2021, pp. 177-180.

X. Zhang, D. Connelly and P. Zheng, "Analysis of 7/8-nm bulk-Si FinFET technologies for 6T-SRAM scaling", IEEE Trans. Electron Devices, vol. 63, no 4, pp. 1502-1507, 2016.

S. Gupta, V. Moroz and L. Smith, "7-nm FinFET CMOS design enabled by stress engineering using Si, Ge, and Sn", IEEE Trans. Electron Devices, vol. 61, no. 5, pp. 1222-1230, 2014.

N. Maity, R. Maity and S. Maity, "Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation", J. Comput. Electron., vol. 18, no 2, pp. 492-499, 2019.

E. Sicard and L. Trojman, "Introducing 5-nm FinFET technology in Microwind", HAL open science, hal-0325444, 2021.

N. Bourahla, A. Bourahla and B.Hadri, "Comparative performance of the ultra-short channel technology for the DG-FinFET characteristics using different high-k dielectric materials" , Indian J. Phys., vol. 95, pp. 1977-1984, 2020.

N. Weste and D. Harris, CMOS VLSI design: a circuits and systems perspective, Pearson Education India, 2015.

J. Baker, CMOS Circuit, Design, Layout and Simulation, IEEE Press Series on Microelectronic Systems, pp. 332-375, 2010.

Y. Eng, L. Hu, T. Chang, S. Hsu, C. Chiou, T. Wang and C. Yang, "Importance of $Delta V_ {{text {DIBLSS}}}/({I} _ {{text {on}}}/{I} _ {{text {off}}}) $ in Evaluating the Performance of n-Channel Bulk FinFET Devices", IEEE J. Electron Devices Soc., pp.207-213, 2018.

M. Lundstrom, Fundamentals of Nanotransistors, World Scientific Publishing Company, vol. 6, 2017 pp. 100-300.

N. Collaert, High mobility materials for CMOS applications, Woodhead Publishing, 2018, pp. 115-280.

Y. Chauhan, D. Lu and S.Venugopalan, FinFET modeling for IC simulation and design: using the BSIM-CMG standard, Academic Press, 2015, pp 72-200.

M. Tang, F. Pregaldiny and C. Lallement, "Quantum compact model for ultra-narrow body FinFET", In Proceedings of the 10th International IEEE Conference on Ultimate Integration of Silicon, 2009, pp. 293-296.

E. Sicard, "Introducing 20 nm technology in Microwind", HAL open science, hal-03324322, pp.3-20, 2011.

E. Sicard and S. Dhia, "Microwind & Dsch: Version 3". INSA, pp.1-90, 2004.

R. Sharma and S.Verma, "Comparitive analysis of static and dynamic cmos logic design", In Proceedings of the IEEE International Conference on Computing and Communication Technologies, 2011, pp. 231-234.

T. Dash, S. Dey and S. Das, "Performance comparison of strained-SiGe and bulk-Si channel FinFETs at 7 nm technology node ", J. Micromech. Microeng., vol. 29, no. 10, p. 104001, 2019.

L. Artola, G.Hubert and M.Alioto,"Comparative soft error evaluation of layout cells in FinFET technology" Microelectron. Reliab., vol. 54, no. 9-10, pp. 2300-2305 ,2014.

V. Vashishtha and L. Clark ,"Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node", Microelectron. J., vol. 107, p. 104942, 2021.

S. Liu, J. Yang and L. Xu, "Can ultra-thin Si FinFETs work well in the sub-10 nm gate-length region? ", Nanoscale, vol. 13, no 10, pp. 5536-5544, 2021.

D. Tripathy, D.Acharya and P.Rout, "Influence of oxide thickness variation on analog and RF performances of SOI FinFET", FU: Elec. Energ., vol. 35, no. 1, pp. 001-011, 2022.

A. Lazzaz, K. Bousbahi and M. Ghamnia, "Optimized mathematical model of experimental characteristics of 14 nm TG N FinFET", Micro and Nanostructures, p. 207210, 2022.

N. Bourahla, B. Hadri and N. Boukortt, "Impact of High-k Dielectric Material on Ultra-Short-DG-FinFET Performance", In Proceedings of the 15th International IEEE Conference on Advanced Technologies, Systems and Services in Telecommunications (TELSIKS), 2021, pp. 78-81.

U. Das, M. Hussain, "Benchmarking silicon FinFET with the carbon nanotube and 2D-FETs for advanced node CMOS logic application", IEEE Trans. Electron Devices, vol. 68, no 7, pp. 3643-3648,2021.

R. Vallabhuni, D. Sravya and M. Shalini, "Design of Comparator using 18nm FinFET Technology for Analog to Digital Converters", In Proceedings of the 7th International IEEE Conference on Smart Structures and Systems (ICSSS), 2020, pp. 1-6.

J. Jena, D. Jena and E. Mohapatra,"FinFET-Based Inverter Design and Optimization at 7 Nm Technology Node", Silicon, vol. 14, pp. 10781-10794, 2022.

S. Sinha, G. Yeric and V. Chandra, "Exploring sub-20nm FinFET design with predictive technology models", In Proceedings of the IEEE DAC Design Automation Conference, 2012, pp. 283-288.

E. Sicard and L. Trojman, "Introducing 5-nm FinFET technology in Microwind", HAL open science, hal-0325444, 2021.

International Roadmap for Devices and Systems. Available at: https://irds.ieee.org/ (2018 Edition).

C. Auth, A. Aliyarukunju and M .Asoro, "A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects", In Proceedings of the IEEE International Electron Devices Meeting (IEDM), 2017 pp. 29.1.1-29.1.4.

P. Vora and R. Lad, "A review paper on CMOS, SOI and FinFET technology", Design and Reuse Industry Articles, p. 1-10, 2017.

M. Tang, F. Prégaldiny and C. Lallement, "Explicit compact model for ultranarrow body FinFETs", IEEE Trans. Electron Devices, vol. 56, no. 7, pp. 1543-1547,2009.

J. Hu and X. Yu, "Near-threshold full adders for ultra low-power applications", In Proceedings of the Second IEEE Pacific-Asia Conference on Circuits, Communications and System, 2010, p. 300-303.

S. Panchanan, R. Maity and S. Baishya, "A surface potential model for tri-gate metal oxide semiconductor field effect transistor: analysis below 10 nm channel length", Eng. Sci. Technol. Int. J., vol. 24, no. 4, pp. 879-889, 2021.

B. Vandana, D. Kumar and S. Mohapatra, "Impact of channel engineering (si1-0.25 ge0.25) technique on gm (transconductance) and its higher order derivatives of 3d conventional and wavy junctionless finfets (jlt)", Facta Universitatis, Series Electronics and Energetics, vol. 31, no. 2, pp. 257-265, 2018.

N. Maity, R. Maity and S.BAISHYA, "An analytical model for the surface potential and threshold voltage of a double-gate heterojunction tunnel FinFET", J. Comput. Electron., vol. 18, no 1, pp. 65-75, 2019.

S. Panchanan, R. Maity, "Modeling, simulation and analysis of surface potential and threshold voltage: application to high-K material HfO2 based FinFET", Silicon, vol. 13, no. 10, pp. 3271-3289, 2021.

S. Panchanan, R. Maity and S. Baishya, "Modeling, Simulation and Performance Analysis of Drain Current for Below 10 nm Channel Length Based Tri-Gate FinFET", Silicon, vol. 14, pp. 11519-11530, 2022.

L. Wang, Y. Chang and K. Cheng, Electronic design automation: synthesis, verification, and test, Morgan Kaufmann (ed), 2009.

S. Shaheen, G. Golan, M. Azoulay, "A comparative study of reliability for FINFET", Facta Universitatis, Series Electronics and Energetics, vol. 31, no 3, pp. 343-366, 2018.

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