ASYNCHRONOUS MONOTONIC MULTIPLEXER

Padmanabhan Balasubramanian, Nikos E Mastorakis

DOI Number
https://doi.org/10.2298/FUEE2502239B
First page
239
Last page
261

Abstract


Among input-output (IO) mode asynchronous circuits, indicating circuits are more popular and robust. However, they may not be efficient in design metrics such as cycle time, area, and power dissipation. In contrast, monotonic circuits, which are also IO mode asynchronous circuits but less explored, can potentially optimize the design metrics better than indicating circuits. Recent studies have demonstrated that monotonic circuits outperform indicating circuits in arithmetic operations like addition and multiplication. While monotonic circuits may be labeled theoretically less robust than indicating circuits, their operation is similar in practice. This article presents a novel, compact monotonic IO mode asynchronous multiplexer. The multiplexer is significant in digital circuits as it has applications across various domains including communication systems, digital signal processing, memory addressing, etc. We considered dual-rail encoding for the multiplexer and employed four-phase handshaking. Two four-phase handshaking schemes are available namely, return-to-zero (RtZ) handshaking and return-to-one (RtO) handshaking, and we considered both for this work. Compared to an optimized early output quasi-delay-insensitive multiplexer, which is derived by modifying a strong-indication multiplexer and represents the best among the existing designs, the proposed monotonic multiplexer achieves a 67% (69%) reduction in latency, an 84% (84%) reduction in area, and a 66% (67%) reduction in power for RtZ (RtO) handshaking. Since the multiplexer is a small component, its effectiveness should be evaluated by integrating it into a circuit setup. In this context, we used existing multiplexers and the proposed multiplexer to realize IO mode asynchronous 32-bit carry select adders (CSLAs) while keeping the compute element, namely the full adder consistent. We estimated the design metrics of CSLAs incorporating different multiplexers, implemented using a 28-nm bulk CMOS process technology. The CSLA utilizing the proposed monotonic multiplexer achieved a 43% (44%) reduction in cycle time and a 28% (28%) reduction in area compared to the CSLA utilizing an early output quasi-delay-insensitive multiplexer for RtZ (RtO) handshaking with no power penalty.


Keywords

asynchronous circuits, digital logic design, low power, high-speed, CMOS

Full Text:

PDF

References


J. Sparsø and S. B. Furber, Principles of Asynchronous Circuit Design: A Systems Perspective. Dordrecht: Kluwer Academic Publishers, 2001.

S. M. Nowick and M. Singh, "Asynchronous Design – Part 1: Overview and Recent Advances", IEEE Design & Test, vol. 32, pp. 5-18, June 2015.

C. H. Van Berkel, M. B. Josephs and S. M. Nowick, "Applications of Asynchronous Circuits", Proc. IEEE, vol. 87, pp. 223-233, Feb. 1999.

A. J. Martin and M. Nystrom, "Asynchronous Techniques for System-on-Chip Design", Proc. IEEE, vol. 94, pp. 1089-1120, June 2006.

I. David, R. Ginosar and M. Yoeli, "Self-timed is Self-Checking", J. Electron. Test.: Theory Appl., vol. 6, pp. 219-228, Apr. 1995.

G. F. Bouesse, G. Sicard, A. Baixas and M. Renaudin, "Quasi Delay Insensitive Asynchronous Circuits for Low EMI", In Proceedings of the 4th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2004, pp. 27-31.

Z. Yu, S. B. Furber and L. A. Plana, "An Investigation into the Security of Self-Timed Circuits", In Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2003, pp. 206-215.

L. A. Plana, P. A. Riocreux, W. J. Bainbridge, A. Bardsley, S. Temple, J. D. Garside and Z. C. Yu, "SPA – A Secure Amulet Core for Smartcard Applications", Microprocess. Microsyst., vol. 27, pp. 431-446, Oct. 2003.

A. J. Martin, "The Limitation to Delay-Insensitivity in Asynchronous Circuits" In Beauty Is Our Business; Texts and Monographs in Computer Science; Feijen, W.H.J., van Gasteren, A.J.M., Gries, D., Misra, J., Eds.; Springer: New York, USA, 1990.

A. J. Martin and P. Prakash, "Asynchronous Nano-Electronics: Preliminary Investigation", In Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008, pp. 58-68.

C. L. Seitz, "System Timing" In Introduction to VLSI Systems; Mead, C., Conway, L., Eds.; Addison-Wesley: Reading, MA, USA, 1980.

C. Brej, Early Output Logic and Anti-Tokens. Ph.D. Thesis, The University of Manchester, UK, September 2005.

K. S. Stevens, R. Ginosar and S. Rotem, "Relative Timing", IEEE Trans. VLSI Syst., vol. 11, pp. 129-140, Feb. 2003.

J. Cortadella, A. Kondratyev, L. Lavagno and C. Sotiriou, "Coping with the Variability of Combinational Logic Delays", In Proceedings of the IEEE International Conference on Computer Design, 2004, pp. 1-4.

V. I. Varshavsky, "Aperiodic Circuits", In Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems; Varshavsky, V.I., (Ed.), (Translated from the Russian by A.V. Yakovlev), Kluwer Academic Publishers: New York, USA, 1990.

P. Balasubramanian and W. Liu, "High-Speed and Energy-Efficient Asynchronous Carry Look-Ahead Adder", PLOS ONE, vol. 18, p. e0289569, Oct. 2023.

P. Balasubramanian and N.E. Mastorakis, "Speed, Power and Area Optimized Monotonic Asynchronous Array Multipliers", J. Low Power Electron. Appl., vol. 14, p. 1, Jan. 2024.

D. E. Muller and S. Bartky, "A Theory of Asynchronous Circuits", In Proceedings of the International Symposium on the Theory of Switching (Part I), 1957, pp. 204-243.

P. A. Beerel, R. O. Ozdag and M. A. Ferretti, A Designer’s Guide to Asynchronous VLSI, Cambridge: Cambridge University Press, 2010.

M. Shams, J. C. Ebergen and M. I. Elmasry, "A Comparison of CMOS Implementations of an Asynchronous Circuits Primitive: The C-element", In Proceedings of the International Symposium on Low Power Electronics and Design, 1996, pp. 93-96.

L. S. Heck, M. T. Moreira and N. L. V. Calazans, "Hardening C-elements against Metastability", In Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017, pp. 314-317.

T. Verhoeff, "Delay-Insensitive Codes – An Overview", Distrib. Comput., vol. 3, pp. 1-8, Mar. 1988.

B. Bose, "On Unordered Codes", IEEE Trans. Comput., vol. 40, pp. 125-131, Feb. 1991.

M. T. Moreira, R. A. Guazzelli and N. L. V. Calazans, "Return-to-one Protocol for Reducing Static Power in C-elements of QDI Circuits Employing M-of-N Codes", In Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012, pp. 1-6.

J. Sparsø and J. Staunstrup, "Delay-Insensitive Multi-Ring Structures", Integr. VLSI J., vol. 15, pp. 313-340, Oct. 1993.

T. Sasao, Switching Theory for Logic Synthesis, Dordrecht: Kluwer Academic Publishers, 1999.

P. Balasubramanian, "Comparative Evaluation of Quasi-Delay-Insensitive Asynchronous Adders Corresponding to Return-to-zero and Return-to-one Handshaking", FU: Elec. Ener., vol. 31, no. 1, pp. 25-39, 2018.

W. B. Toms, Synthesis of Quasi-Delay-Insensitive Datapath Circuits, Ph.D. Thesis, The University of Manchester, UK, February 2006.

W. B. Toms and D. A. Edwards, "Indicating Combinational Logic Decomposition", IET Comput. Digit. Tech., vol. 5, pp. 331-341, July 2011.

R. K. Brayton, G. D. Hachtel, C. T. McMullen and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Springer: New York, 1984.

R. Rudell, Logic Synthesis for VLSI Design, Ph.D. Thesis, University of California, Berkeley, USA, 1989.

P. Balasubramanian and D.A. Edwards, "Power, Delay and Area Efficient Self-Timed Multiplexer and Demultiplexer Designs", In Proceedings of the 4th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2009, pp. 173-178.

Synopsys Databook, Synopsys SAED_EDK32/28_CORE Databook, Revision 1.0.0. January 2012.

O. J. Bedrij, "Carry-Select Adder", IRE Trans. Electron. Comput., vol. EC-11, pp. 340-346, June 1962.

P. Balasubramanian, "Asynchronous Carry Select Adders", Eng. Sci. Technol. Int. J., vol. 20, pp. 1066-1074, June 2017.

P. Balasubramanian, "A Robust Asynchronous Early Output Full Adder", WSEAS Trans. Circ. Syst., vol. 10, pp. 221-230, July 2011.

P. Balasubramanian and S. Yamashita, "Area/Latency Optimized Early Output Asynchronous Full Adders and Relative-Timed Ripple Carry Adders”, SpringerPlus, vol. 5, p. 440, Apr. 2016.

J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits: A Design Perspective, 2nd ed.; London: Pearson Education, 2003.


Refbacks

  • There are currently no refbacks.


ISSN: 0353-3670 (Print)

ISSN: 2217-5997 (Online)

COBISS.SR-ID 12826626