DESIGN OF A SCPLL FOR APPLICATION IN DISTRIBUTED FREQUENCY BANDS

Mriganka Gogoi, Pranab Kishore Dutta

DOI Number
https://doi.org/10.2298/FUEE2502289G
First page
289
Last page
304

Abstract


The manuscript presents the design of a Switched Controlled Phase Locked Loop (SCPLL), a pivotal component in communication systems. Comprising a Phase Frequency Detector (PFD), Charge Pump (CP), Low Pass Filter (LPF), and Voltage Controlled Oscillator (VCO), the PLL is instrumental in maintaining precise signal synchronization. This novel SCPLL incorporates a versatile Phase Locked Loop architecture. The VCO noteworthy feature is its ability to operate within distributed frequency bands, Lower band (LB) and Upper band (UB), specifically ranging from 45 MHz to 600 MHz and 850 MHz to 1.04 GHz. Higher-order low pass filters is demonstrated to be highly effective in reducing unwanted spurious emissions, thereby enhancing signal purity. The Switched Controller (SC) within this system offers the ability to select the desired frequency band and filter order, providing adaptability and control over system performance. Spur reduction is found to be approximately -4 dBc in UB while negligible difference in LB on replacing first order filter by 2nd order filter. The experimental Phase noise value of the proposed SCPLL is estimated to be -93.15 dBc/Hz at 1MHz and -118.79 dBc/Hz at 10 MHz respectively. Power Consumption of the circuit is found to be 1.8 mw with an area of 0.0023 mm2. In terms of efficiency, the circuit demonstrates an impressive tradeoff between the frequency of operation, phase noise, spur reduction and power.


Keywords

Switched Controlled (DSC); Phase Locked Loop (PLL); Tuning Range; Spur

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References


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