STRUCTURAL DESIGN AND PERFORMANCE ANALYSIS OF DOUBLE GATE POCKET TFET FOR LOW POWER APPLICA-TIONS

Manish Verma, Pradipta Dutta, Arindam Basak, Ramesh Kumar Meena

DOI Number
https://doi.org/10.2298/FUEE2503375V
First page
375
Last page
395

Abstract


This research investigates Tunnel Field Effect Transistors (TFETs), a paradigm shift in low-power electronics, leveraging band-to-band tunneling for superior subthreshold slope and reduced power dissipation compared to conventional MOSFETs. We elucidate the underlying physics of TFET operation, analyzing the interplay between device geometry, material properties, and band structure engineering. A comprehensive analysis of key performance metrics, including on-current, off-current, and subthreshold swing, is conducted, considering the impact of critical device parameters. Furthermore, this work presents a novel vertical TFET architecture demonstrating enhanced performance and scalability compared to conventional planar devices. The vertical structure minimizes parasitic resistances and enables efficient band-to-band tunneling, leading to significant improvements in device characteristics. Challenges associated with both conventional and vertical TFETs, including material integration and performance limitations, are critically examined alongside potential mitigation strategies. The potential applications of TFETs are explored across diverse domains, including low-power digital circuits, RFICs, and neuromorphic computing, highlighting their significance in addressing the escalating demand for energy-efficient electronics in the era of AI and IoT. Finally, future research directions, emphasizing the need for interdisciplinary collaboration and innovative approaches to materials, device engineering, and circuit design, are outlined to unlock the full potential of TFETs in shaping the future of electronics.


Keywords

TFET, MOSFET, DG-TFET, Junction less TFET, Doping less PNPN TFET, LVTSCR (Low-Voltage Trigger SCR)

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References


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