DESIGN OF LOW POWER CURRENT STARVED RING OSCILLATORS USING MODIFIED PARTICLE SWARM OPTIMIZATION

Sandeep Kumar Dash, Bishnu Prasad De, Bhargav Appasani, Nirmal Kumar Rout

DOI Number
https://doi.org/10.2298/FUEE2504625D
First page
625
Last page
637

Abstract


Ring oscillators (RO) are widely used for clock generation in RF applications. Design of RO is a very tedious process for RF IC designers using traditional methods like hand calculation or by simulator assistance. Traditional evolutionary optimization techniques, such as Particle swarm optimization (PSO) can be utilized for the design of the ROs. However, it shows limitations in convergence and stagnation. In this work to overcome these problems, PSO with Constriction Factor and Inertia Weight Approach (PSO-CFIWA) is applied to design a Current-starved Ring oscillator (CSRO). The optimum size of the CSRO transistors is obtained from PSO-CFIWA and designed in Cadence spectre using GPDK 90nm technology. The objective of the CSRO design is to have a 2 GHz oscillation frequency with optimized phase noise, power consumption, and figure of merit (FOM). The designed CSRO shows a 1.99963 GHz oscillation frequency, 348.48 µW power dissipation, –86.67 dBc/Hz phase noise, and FOM of – 157.25. The simulation results establish the effectiveness of PSO-CFIWA with its counterparts in RO design.


Keywords

ring oscillator, current starved ring oscillator, FOM, phase noise, cadence

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References


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