A DOUBLE-DIFFERENTIAL-INPUT /DIFFERENTIAL-OUTPUT FULLY COMPLEMENTARY AND SELF-BIASED ASYNCHRONOUS CMOS COMPARATOR
Abstract
Full Text:
PDFReferences
T. Sepke et al., “Comparator-based switched-capacitor circuits for scaled CMOS technologies,” in ISSCC Dig. Tech.Papers, Feb. 2006, pp. 812–821.
D. Schinkel et al., “A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time,” in ISSCC Dig. Tech.Pap., Feb. 2007, pp. 314–315.
V. Srinivasan et al., “A 20mW 61 dB SNDR (60MHz BW) 1 b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45 nm CMOS,” in ISSCC Dig. Tech.Papers, Feb. 2012, pp. 812–821.
C.-Y. Yang and S.-I. Liu, “A one-wire approach for skew-compensating clock distribution based on bidirectional techniques,” IEEE Journal of Solid-State Circuits, vol. 36, no. 2, pp. 266–272, Feb. 2001.
M.-C. Huang and S.-I. Liu, “A fully differential comparator-based switched-capacitor __ modulator,” IEEE Transactions on Circuits and Systems II: Express
Briefs, vol. 56, no. 5, pp. 369–373, May 2009.
M. Bazes, “Two novel fully complementary self-biased CMOS differential amplifiers,” IEEE J. of Solid-State Circuits, vol. 26, no. 2, pp. 165–168, Feb. 1991.
B. J. McCarroll et al., “A high-speed CMOS comparator for use in an ADC,” IEEE Journal of Solid-State Circuits, vol. 23, no. 1, pp. 159–165, Feb. 1988.
Refbacks
- There are currently no refbacks.
ISSN: 0353-3670 (Print)
ISSN: 2217-5997 (Online)
COBISS.SR-ID 12826626