DESIGN AND PERFORMANCE ANALYSIS OF FULL ADDER USING 6-T XOR–XNOR CELL

K Srinivasa Rao, Marupaka Aditya, B.S.D. Karthik Raja, CH. Manisai, M Tharun Sai Reddy, K. Girija Sravani

DOI Number
https://doi.org/10.2298/FUEE2202187R
First page
187
Last page
198

Abstract


In this paper, the design and simulation of a high-speed, low power 6-T XOR-XNOR circuit is carried out. Also, the design and simulation of 1-bit hybrid full adder (consisting of 16 transistors) using XOR-XNOR circuit, sum, and carry, is performed to improve the area and speed performance. Its performance is being compared with full adder designs with 20 and 18 transistors, respectively. The performance of the proposed circuits is measured by simulating them in Microwind tool using 180 and 90nm CMOS technology. The performance of the proposed circuit is measured in terms of power, delay, and PDP (Power Delay Product).


Keywords

XOR-XNOR circuit, Hybrid full adder

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References


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