REALIZATION OF A VARIABLE RESOLUTION MODIFIED SEMIFLASH ADC BASED ON BIT SEGMENTATION SCHEME

Pranati Ghoshal, Chanchal Dey, Sunit Kumar Sen

DOI Number
https://doi.org/10.2298/FUEE2201061G
First page
061
Last page
070

Abstract


A modified variable resolution semiflash ADC, based on ‘bit segmentation scheme’, is presented. Its speed and comparator count are identical to a normal flash ADC. An 8-bit ADC has 256 different bit combinations. Sixteen consecutive bit combinations from the MSB side – beginning with the first one, remain unaltered for such an ADC. It continues this way till the last group of sixteen bits. In the designed circuit, the four MSB and four LSB bits are determined in the first and second part of the clock. Following the same logic, the bits in a 16-bit ADC can be found out in only two clock cycles by employing only fifteen comparators. It implies that a higher resolution ADC can easily be determined with low power and small die area. It is tested in P-SIM Professional 9 for an 8-bit ADC and curves drawn to establish the validity of the proposal.


Keywords

Bit segmentation scheme (BSS), bit swap logic (BSL), least significant bit (LSB), semiflash ADC, half flash ADC, modified full flash ADC (MFFADC)

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References


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ISSN: 0353-3670 (Print)

ISSN: 2217-5997 (Online)

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