PARALLEL EXECUTION TRACING: AN ALTERNATIVE SOLUTION TO EXPLOIT UNDER-UTILIZED RESOURCES IN MULTI-CORE ARCHITECTURES FOR CONTROL-FLOW CHECKING
Abstract
In this paper, a software behavior-based technique is presented to detect control-flow errors in multi-core architectures. The analysis of a key point leads to introduce the proposed technique: employing under-utilized CPU resources in multi-core processors to check the execution flow of the programs concurrently and in parallel with the main executions. To evaluate the proposed technique, a quad-core processor system was used as the simulation environment, and the behavior of SPEC CPU2006 benchmarks were studied as the target to compare with conventional techniques. The experimental results, with regard to both detection coverage and performance overhead, demonstrate that on average about 94% of the control-flow errors can be detected by the proposed technique, more efficiently.
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S. Kumar, S. Hari, M. Li, P. Ramachandran, B. Choi and S. V. Adve, “mSWAT: Low-Cost Hardware Fault Detection and Diagnosis for Multicore Systems,” In Proc of the 42th Annual International Symposium on Microarchitecture, 2009.
G. A. Reis, J. Chang, N. Vachharajani, R. Rangan and D. I. August, “SWIFT: Software Implemented Fault Tolerance,” In Proc. of the 3rd International Symposium on Code Generation and Optimization, 2005, pp. 243-254.
W. Shi, H. Hsin, S. L. Laura Falk and M. Ghosh, “An Integrated Framework for Dependable and Revivable Architecture Using Multicore Processors,” In Proc. of the 33th Annual International Symposium on Computer Architecture, 2006.
N. Aggarwal, P. Ranganathan, N. Jouppi and J. Smith, “Configurable Isolation: Building High Availability Systems with Commodity Multi-Core Processors,” In Proc. of the 34th Annual International Symposium on Computer Architecture, 2007, pp. 340-347.
M. Manoochehri, M. Annavaram and M. Dubois, “CPPC: Correctable Parity Protected Cache,” In Proc. of the 44th Annual International Symposium on Microarchitecture, 2011.
T. Slegel, R. Averill III, M. Check, B. Giamei, B. Krumm, C. Krygowski, W. Li, J. Liptay, J. MacDougall, T. McPherson, J. Navarro, E. Schwarz, K. Shum, and C. Webb, “IBM’s S/390 G5 Microprocessor design,” IEEE Micro, vol. 19, pp. 12–23, 1999.
B. F. Romanescu and D. J. Sprin, “Core Cannibalization Architecture: Improving Lifetime Chip Performance for Multicore Processors in the Presence of Hard Faults,” In Proc. of the 17th International Conference on Parallel Architecture and Compilation Techniques, 2008, pp. 43-50.
M. D. Powell, A. Biswas, S. Gupta and S. S. Mukherjee, “Architectural Core Salvaging in a Multi-Core Processor for Hard-Error Tolerance,” In Proc. of the 36th Annual International Symposium on Computer Architecture, 2009, pp. 93-104.
P. M.Wells, K. Chakraborty and G. S. Sohi, “Mixed-Mode Multicore Reliability,” In Proc. of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009, pp. 169-180.
H. Aliee, H. R. Zarandi and A. Tajary, “Dynamically Scheduled Process-Level Redundancy to Tolerate Faults in Multi-cores,” In Proc. of the 9th IEEE International Conference on High Performance Computing & Simulation, 2011.
A. Meixner and D. J. Sorin, “Detouring: Translating Software to Circumvent Hard Faults in Simple Cores,” In Proc. of the 38th IEEE/IFIP International Conference on Dependable Systems and Networks, 2008 pp. 80-89.
A. Shye, T. Moseley, V. J. Reddi, J. Blomstedt and D. A. Connors, “Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance,” In Proc. of the 37th IEEE/IFIP International Conference on Dependable Systems and Networks, 2007.
A. Shye, J. Blomstedt, T. Moseley, V. J. Reddi and D. A. Connors, “PLR: A Software Approach to Transient Fault Tolerance for Multi-Core Architectures,” IEEE Transactions on Dependable and Secure Computing, 2008.
M. Fazeli, R. Farivar and G. Miremadi, “Error Detection Enhancement in PowerPC Architecture-based Embedded Processors,” Journal of Electronic Testing: Theory and Applications, vol. 24, pp. 21-33, 2008.
R. Vemu and J. A. Abraham, “CEDA: Control-flow Error Detection through Assertions,” In Proc. of the 12th IEEE International On-Line Testing Symposium, 2006, pp. 151–158. [16] N. Oh, P. Shirvani and E. McCluskey, “Control-flow Checking by Software Signatures,” IEEE Transactions on Reliability, vol. 51, pp. 111–122, 2002.
O. Goloubeva, M. Rebaudengo, M. Sonza Reorda and M. Violante, “Improved Software-Based Processor Control-Flow Errors Detection Technique,” In Proc. of the 50th Reliability and Maintainability Syposium, 2005, pp. 583-589.
R. Vemu, S. Gurumurthy and J. A. Abraham, “ACCE: Automatic Correction of Control-flow Errors,” In Proc. of the IEEE International Test Conference, 2007, pp. 1-10.
G. Blake, R. G. Dreslinski, T. Mudge, K. Flautner, “Evolution of Thread-Level Parallelism in DesktopApplications,” In Proc. of the 43th Annual International Symposium on Microarchitecture, ISCA, 2010.
M. Rimén, J. Ohlsson and J. Karlsson, “Experimental evaluation of control flow errors,” In Proc. of the Pacific Rim International Symposium on Fault Tolerant Systems, 1995, pp. 238–243.
M.A. Schuette, J.P. Shen, "Processor Control Flow Monitoring Using Signatured Instruction Streams," IEEE Transactions on Computers, vol. 36, pp. 264-276, 1987.
A. Rajabzadeh and G. Miremadi, “Transient detection in COTS processors using software approach,” Journal of Microelectronics Reliability, vol. 46, pp. 124-133, 2006.
A. Rajabzadeh, G. Miremadi and M. Mohandespour, “Error detection enhancement in COTS superscalar processors with performance monitoring features,” Journal of Electronic Testing: Theory and Applications, vol. 20, pp. 553-567, 2004.
A. Rajabzadeh and G. Miremadi, “CFCET: A Hardware-Based Control Flow Checking Technique in COTS Processors Using Execution Tracing,” Elsevier Journal of Microelectronics Reliability, vol. 46, pp. 959-972, 2006.
U. Schiffel, A. Schmitt, M. Süßkraut and C. Fetzer, “ANB- and ANBDmem-Encoding: Detecting Hardware Errors in Software,” In Proc. of the 29th International Conference on Computer Safety, Reliability and Security, 2010, pp. 169-182.
H. R. Zarandi, M. Maghsoudloo and N. Khoshavi,“Two Efficient Software Techniques to Detect and Correct Control-flow Errors,” In Proc. of the 16th IEEE Pacific Rim International Symposium on Dependable Computing,2010, pp. 141-148.
M. Maghsoudloo, H.R. Zarandi, S. Pour-Mozaffari and N. Khoshavi, “Soft Error Detection Technique in Multi-threaded Architectures Using Control-Flow Monitoring,” In Proc. of the 14th Euromicro Conference on Digital System Design, Architecture, Methods and Tools, 2011.
E. D. Berger, T. Yang, T. Liu and G. Novark, “Grace: Safe Multithreaded Programming for C/C++,” In Proc. of the 24th SIGPLAN Conference on Object Oriented Programming Systems Languages and Applications, 2009, pp.81-96.
David Patterson, “The Trouble with Multi-Core,” Journal of IEEE Spectrum, vol. 47, pp. 28-32, 2010.
Standard Performance Evaluation Corporation. SPEC CPU2006 Benchmarks, http://www.specbench.org/ cpu2006, 2006.
Sh. Parsaeeian, and A. Rajabzadeh, “Multi-Bit Upset Faults Correction in Embedded Systems”, Journal of Iran Computer Society, 2011.
GDB: The GNU Project Debugger, http://www.gnu.org/s/gdb.
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