Sengupta, Anirban, Computer Science and Engineering, Indian Institute of Technology Indore, India, India

• Vol 27, No 2 (2014) - INVITED PAPERS
  EXECUTION TIME – AREA TRADEOFF IN GAUSING RESIDUAL LOAD DECODER: INTEGRATED EXPLORATION OF CHAINING BASED SCHEDULE AND ALLOCATION IN HLS FOR HARDWARE ACCELERATORS
  Abstract  PDF

ISSN: 0353-3670 (Print)

ISSN: 2217-5997 (Online)

COBISS.SR-ID 12826626