Milena Stanojlović Mirković, Miljana Milić, Dejan Mirković

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This paper deals with a top down design of an example multiplexer cell that exhibits high immunity to Side Channel Attack (SCA). Four different solutions of the encrypted multiplexer cell are revised, and the best design adopted. The post-layout simulations prove resistance of the multiplexer logic cell to the SCA. Since the physical layout structure and the functionality of this kind of design is based on symmetry, concerns were expressed as to what will be the effectiveness of the method under real production conditions. To get a proper answer to that, the adequacy of the chosen design for the multiplexer cell, which uses the "No Short-circuit Current Dynamic Differential Logic" (NSDDL) method, is confirmed by observing a Normalized Standard Deviation (NSD).


CMOS integrated circuits, encrypted cell, layout, electrical and post-layout simulation, SCA

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V. Borović, S. Borović, V. Drąsutė, D. Rančić, “Secure organ transplant information system”, Facta Universitatis, Series: Automatic Control and Robotics, vol. 17, no. 1, pp. 1-12, 2018.

E. Dubrova, “Energy-Efficient cryptographic primitives”, Facta Universitatis, Series: Electronics and Energetics, vol. 31, no. 2, pp. 157-167, 2018.

S. Hong, Special Issue on “Side Channel Attacks”, Applied Sciences, vol. 9, no. 9, pp. 1-6, 2019. doi.org/10.3390/app9091881

M. Stanojlovic, P. Petkovic, “ Strategies against side-channel-attack” in Proceedings of the Small Systems Simulation Symposium, Niš, Serbia, pp. 86–89, 2010.

C. Monteiro, Y. Takahashi, T. Sekine, “Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level”, Microelectronics Journal, Elsevier, vol. 44, no. 6, pp. 496-503, 2013. doi.org/10.1016/j.mejo.2013.04.003

P. Kocher, J. Jaffe, B. Jun, “Differential power analysis”, Advances in Cryptology (CRYPTO'99), California, USA, pp. 388-406, 1999.

K. Tiri, I. Verbauwhede, “A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation", Design, Automation and Test in Europe Conference (DATE 2004), pp. 246-251, 2004.

J. Quan, G. Bai, “A new method to reduce the side-channel leakage caused by unbalanced capacitances of diferential interconnections in dual rail logic styles”, Sixth International Conference on Information Technology: New Generations, pp. 58-63, 2009.

H. Marzouqi, M. Al-Qutayri and K. Salah, Review of gate-level differential power analysis and fault analysis countermeasures, in IET Information Security, vol. 8, no. 1, pp. 51-66, 2014. doi: 10.1049/ietifs.2012.0319

R. Velegalati, “Securing Light Weight Cryptographic Implementations on FPGAs Using Dual Rail with Pre-Charge Logic” PhD Thesis, George Mason University, Fairfax, VA, 2009.

M. Stanojlovic, P. Petkovic, “Hardware based strategies against side-channel-attack implemented in WDDL” Electronics, vol. 14, no. 1, pp. 117-122, 2010.

E. Amouri, H. Mehrez, Z. Marrakchi, “Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA”, International Journal of Reconfigurable Computing, vol. 2013, ID. 802436, pp. 24, 2013. http://dx.doi.org/10.1155/2013/802436

H. Kim,, V. Rozic, I. Verbauwhede, “Three Phase Dynamic Current Mode Logic A More Secure DyCML” to Achieve a More Balanced Power Consumption’, 13th International Workshop, WISA 2012, Jeju Island, Korea, pp. 68-81, 2012.

M. Bucci, L. Giancane, R. Luzzi, A. Trifiletti, “Three-Phase Dual-Rail Pre-charge Logic”. In: L. Goubin and M. Matsui, Cryptographic Hardware and Embedded Systems - CHES 2006 (Springer, Berlin, Heidelberg 2006), pp. 232-241, 2006. doi.org/10.1007/11894063_19

Mentor Graphics, ASIC Design Kit, 2007.

X. Linfu, E. F. Young, H. Xiaoyong, K. P. Pun, “Practical placement and routing techniques for analog circuit designs”, in Proceedings of the International Conference on Computer-Aided Design, San Jose, California, pp. 675-679, 2010.

T. Wenyi, J. Song and W. Yuan, “Dual-Voltage Single-Rail Dynamic DPA-Resistant Logic Based on Charge Sharing Mechanism”, Chinese Journal of Electronics, vol. 26, no. 6, pp. 899-904. 2017.

F. Mace, F.-X. Standaert, I. Hassoune, J.-D. Legat, J.-J. Quisquater, “A dynamic current mode logic to counteract power analysis attacks”, in Proceedings of DCIS, pp.186-191, 2004.

P. Wang, Y. Zhang, X. Zhang, “Design of two-phase SABL flip-flop for resistant DPA attacks”, Chinese Journal of Electronics, vol. 22, no.4, pp.833-837, 2013.

M. Stanojlović, V. Litovski, Petković P., “Testiranje standardne AND ćelije otporne na bočne napade”, Zbornik LVIII konferencije ETRAN, Vrnjačka Banja, 02.06.-05.06., EL2.5, 2014.

M. Stanojlović Mirković, V. Litovski, P. Petković, D. Milovanović, “Faults Simulations in XOR/XNOR Cell Resistant to Side Channel Attacks”, X Simposium on Industrial Electronics INDEL, Banja Luka (Bosnia and Herzegovina), pp. 83-88, 2014.

DOI: https://doi.org/10.22190/FUACR1903141S


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