Sushanta K Mohapatra, Kumar P. Pradhan, Prasanna K. Sahu

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The present understanding of this work is about to evaluate and resolve the temperature compensation point (TCP) or zero temperature coefficient (ZTC) point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25 0C to 225 0C is reviewed to extend the benchmark of device scalability. The impact of fin height (HFin), fin width (WFin), and temperature (T) on immense performance metrics including on-off ratio (Ion/Ioff), transconductance (gm), gain (AV), cut-off frequency (fT), static power dissipation (PD), energy (E), energy delay product (EDP), and sweet spot (gmfT/ID) of the FinFET is successfully carried out by commercially available TCAD simulator SentaurusTM from Synopsis Inc.

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S. M. Sze, Physics of Semiconductor Devices, Third Edit. John Wiley and Sons Inc., 2009.

I. M. Filanovsky and A. Allam, “Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits,” Circuits Syst. I Fundam. Theory Appl. IEEE Trans., vol. 48, no. 7, pp. 876–884, 2001.

B. Cheng, M. Cao, R. Rao, A. Inani, P. Vande Voorde, W. M. Greene, J. M. C. Stork, Z. Yu, P. M. Zeitzoff, and J. C. S. Woo, “The impact of high-κ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs,” Electron Devices, IEEE Trans., vol. 46, no. 7, pp. 1537–1544, 1999.

N. S. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and V. Narayanan, “Leakage current: Moore’s law meets static power,” Computer (Long. Beach. Calif)., vol. 36, no. 12, pp. 68–75, 2003.

H. P. Wong, S. Member, D. J. Frank, P. M. Solomon, C. H. J. Wann, and J. J. Welser, “Nanoscale CMOS,” Proc. IEEE, vol. 87, no. 4, pp. 537–570, 1999.

M. Bruel, “Silicon on insulator material technology,” Electron. Lett., vol. 31, no. 14, pp. 1201–1202, 1995.

G. K. Celler and S. Cristoloveanu, “Frontiers of silicon-on-insulator,” J. Appl. Phys., vol. 93, no. 9, pp. 4955–4978, 2003.

G. Reichert, C. Raynaud, O. Faynot, F. Balestra, and S. Cristoloveanu, “Submicron SOI-MOSFETs For High Temperature Operation (300K-600K),” Microelectron. Eng., vol. 36, no. 1–4, pp. 359–362, Jun. 1997.

D.-S. Jeon and D. E. Burk, “A temperature-dependent SOI MOSFET model for high-temperature application (27 °C-300 °C),” IEEE Trans. Electron Devices, vol. 38, no. 9, pp. 2101 – 2111, 1991.

L. Vadasz and A. S. Grove, “Temperature dependence of MOS transistor characteristics below saturation,” IEEE Trans. Electron Devices, vol. 24, no. 12, pp. 863–866, 1966.

B. Lengeler, “Semiconductor devices suitable for use in cryogenic environments,” Cryogenics (Guildf)., vol. 14, no. 8, pp. 439–447, 1974.

E. S. Schlig, “Low-temperature operation of Ge picosecond logic circuits,” Solid-State Circuits, IEEE J., vol. 3, no. 3, pp. 271–276, 1968.

F. H. Gaensslen, V. L. Rideout, E. J. Walker, and J. J. Walker, “Very small MOSFET’s for low-temperature operation,” IEEE Trans. Electron Devices, vol. 24, no. 3, pp. 218–229, 1977.

W. A. Krull and J. C. Lee, “Demonstration of the benefits of SOI for high temperature operation,” in SOS/SOI Technology Workshop, 1988. Proceedings., 1988 IEEE, 1988, p. 69.

G. Groeseneken, J.-P. Colinge, H. E. Maes, J. C. Alderman, and S. Holt, “Temperature dependence of threshold voltage in thin-film SOI MOSFETs,” IEEE Electron Device Lett., vol. 11, no. 8, pp. 329–331, 1990.

T. H. Tan and A. K. Goel, “Zero-Temperature-Coefficient Biasing Point of a Fully depleted SOI MOSFET,” Microw. Opt. Technol. Lett., vol. 37, no. 5, pp. 366–370, 2003.

F. S. Shoucair, “Analytical and experimental methods for zero-temperature-coefficient biasing of MOS transistors,” Electron. Lett., vol. 25, no. 17, pp. 1196 – 1198, 1989.

Z. D. Prijić, S. S. Dimitrijev, and N. D. Stojadinović, “The determination of zero temperature coefficient point in CMOS transistors,” Microelectron. Reliab., vol. 32, no. 6, pp. 769–773, Jun. 1992.

M. Emam, J. C. Tinoco, D. Vanhoenacker-Janvier, and J. P. Raskin, “High-temperature DC and RF behaviors of partially-depleted SOI MOSFET transistors,” Solid. State. Electron., vol. 52, no. 12, pp. 1924–1932, 2008.

A. A. Osman, M. A. Osman, N. S. Dogan, and M. A. Imam, “Zero-temperature-coefficient biasing point of partially depleted SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 42, no. 9, pp. 1709–1711, 1995.

Z. D. Prijić, S. S. Dimitrijev, and N. D. Stojadinović, “Analysis of temperature dependence of CMOS transistors’ threshold voltage,” Microelectron. Reliab., vol. 31, no. 1, pp. 33–37, 1991.

Z. Prijić, Z. Pavlović, S. Ristić, and N. Stojadinović, “Zero-temperature-coefficient (ZTC) biasing of power VDMOS transistors,” Electron. Lett., vol. 29, no. 5, pp. 435–437, 1993.

B. Gentinne, J. P. Eggermont, and J. P. Colinge, “Performances of SOI CMOS OTA combining ZTC and gain-boosting techniques,” Electron. Lett., vol. 31, no. 24, pp. 2092–2093, 1995.

M. El Kaamouchi, M. S. Moussa, J.-P. Raskin, and D. Vanhoenacker-Janvier, “Zero-temperature-coefficient biasing point of 2.4-GHz LNA in PD SOI CMOS technology,” in Microwave Conference, 2007. European, 2007, pp. 1101–1104.

D. Flandre, L. Demeus, V. Dessard, A. Viviani, B. Gentinne, and J.-P. Eggermont, “Design and application of SOI CMOS OTAs for high-temperature environments,” in Solid-State Circuits Conference, 1998. ESSCIRC ’98. Proceedings of the 24th European, 1998, pp. 404–407.

K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling theory for double-gate SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 40, no. 12, pp. 2326–2329, 1993.

C. H. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, “A comparative study of advanced MOSFET concepts,” IEEE Trans. Electron Devices, vol. 43, no. 10, pp. 1742–1753, 1996.

J. P. Colinge, “Multiple-gate SOI MOSFETs,” Solid. State. Electron., vol. 48, no. 6, pp. 897–905, 2004.

H. S. P. Wong, “Beyond the conventional transistor,” IBM J. Res. Dev., vol. 46, no. 2, pp. 133–168, 2002.

P. K. Sahu, S. K. Mohapatra, K. P. Pradhan, P. K. Sahu, S. K. Mohapatra, and K. P. Pradhan, “Impact of Downscaling on Analog/RF Performance of sub-100nm GS-DG MOSFET,” J. Microelectron. Electron. Components Mater., vol. 44, no. 2, pp. 119–125, 2014.

P. K. Sahu, S. K. Mohapatra, and K. P. Pradhan, “A Study of SCEs and Analog FOMs in GS-DG- MOSFET with Lateral Asymmetric Channel Doping,” J. Semicond. Sci., vol. 13, no. 6, pp. 647–654, 2013.

S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Resolving the bias point for wide range of temperature applications in high-k/metal gate nanoscale DG-MOSFET,” Facta Univ. Ser. Electron. Energ., vol. 27, no. 4, pp. 613–619, 2014.

S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics,” Superlattices Microstruct., vol. 78, pp. 134–143, 2015.

P. K. Sahu, S. K. Mohapatra, and K. P. Pradhan, “Zero temperature-coefficient bias point over wide range of temperatures for single-and double-gate UTB-SOI n-MOSFETs with trapped charges,” Mater. Sci. Semicond. Process., vol. 31, pp. 175–183, 2015.

V. A. Sverdlov, T. J. Walls, and K. K. Likharev, “Nanoscale silicon MOSFETs: A theoretical study,” IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1926–1933, 2003.

C. R. Manoj, M. Nagpal, D. Varghese, and V. R. Rao, “Device Design and Optimization Considerations for Bulk FinFETs,” IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 609–615, 2008.

A. Kranti and G. A. Armstrong, “Device design considerations for nanoscale double and triple gate FinFETs,” in Proceedings - IEEE International SOI Conference, 2005, vol. 2005, pp. 96–98.

H. Shang, L. Chang, X. Wang, M. Rooks, Y. Zhang, B. To, K. Babich, G. Totir, Y. Sun, E. Kiewra, M. Ieong, and W. Haensch, “Investigation of FinFET Devices for 32nm Technologies and Beyond,” 2006 Symp. VLSI Technol. 2006. Dig. Tech. Pap., 2006.

B. Ho, X. Sun, C. Shin, and T. Liu, “Design optimization of multigate bulk MOSFETs,” IEEE Trans. Electron Devices, vol. 60, no. 1, pp. 28–33, 2013.

X. Sun, V. Moroz, N. Damrongplasit, C. Shin, and T. J. K. Liu, “Variation study of the planar ground-plane bulk MOSFET, SOI FinFET, and trigate bulk MOSFET designs,” IEEE Trans. Electron Devices, vol. 58, no. 10, pp. 3294–3299, 2011.

M. G. C. De Andrade, J. A. Martino, M. Aoulaiche, N. Collaert, E. Simoen, and C. Claeys, “Behavior of triple-gate Bulk FinFETs with and without DTMOS operation,” Solid. State. Electron., vol. 71, pp. 63–68, 2012.

K. P. Pradhan, S. K. Mohapatra, P. K. Sahu, and D. K. Behera, “Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET,” Microelectronics J., vol. 45, no. 2, pp. 144–151, 2014.

S. Selberherr, Analysis and Simulation of Semiconductor Devices. 1984, pp. Springer–Verlag, Wien–New York.

“The International Technology Roadmap for Semiconductors,” 2011.

C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, “A physically based mobility model for numerical simulation of nonplanar devices,” IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 7, no. 11, pp. 1164 – 1171, 1988.

W. Shockley and W. T. Read, “Statistics of the Recombination of Holes and Electrons,” Phys. Rev., vol. 87, pp. 835–842, 1952.

R. N. Hall, “Electron-Hole Recombination in Germanium,” Phys. Rev., vol. 87, p. 387, 1952.

R. K. Sharma and M. Bucher, “Device design engineering for optimum analog/RF performance of nanoscale DG MOSFETs,” IEEE Trans. Nanotechnol., vol. 11, no. 5, pp. 992–998, 2012.


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