EFFECTS OF PULSED NEGATIVE BIAS TEMPERATURE STRESSING IN P-CHANNEL POWER VDMOSFETS

Ivica Manić, Danijel Danković, Vojkan Davidović, Aneta Prijić, Snežana Djorić-Veljković, Snežana Golubović, Zoran Prijić, Ninoslav Stojadinović

DOI Number
10.2298/FUEE1601049M
First page
49
Last page
60

Abstract


Our recent research of the effects of pulsed bias NBT stressing in p-channel power VDMOSFETs is reviewed in this paper. The reduced degradation normally observed under the pulsed stress bias conditions is discussed in terms of the dynamic recovery effects, which are further assesed by varying the duty cycle ratio and frequency of the pulsed stress voltage. The results are analysed in terms of the effects on device lifetime as well. A tendency of stress induced degradation to decrease with lowering the duty cycle and/or increasing the frequency of the pulsed stress voltage, which leads to the increase in device lifetime, is explained in terms of enhanced dynamic recovery effects.


Keywords

VDMOSFET, NBTI, pulsed bias stress, threshold voltage, lifetime

Full Text:

PDF

References


D.K. Schroder, J.A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing”, J. Appl. Phys., vol. 94, pp. 118, 2003.

J.H. Stathis, S. Zafar, “The negative bias temperature instability in MOS devices: A Review”, Microelectron. Reliab., vol. 46, pp. 270286, 2006.

S. Ogawa, M. Shimaya, N. Shiono, “Interface-trap generation at ultrathin SiO2 (46 nm)-Si interfaces during negative-bias temperature aging”, J. Appl. Phys., vol. 77, pp. 11371148, 1995.

V. Huard, M. Denais, C. Parthasarathy, “NBTI degradation: From physical mechanisms to modeling”, Microelectron. Reliab., vol. 46, pp. 123, 2006.

M.A. Alam, S.A. Mahapatra, “A comprehensive model of PMOS NBTI degradation”, Microelectron. Reliab., vol. 45, pp. 7181, 2005.

S. Mahapatra, N. Goel, S. Desai, S. Gupta, B. Jose, S. Mukhopadhyay, K. Joshi, A. Jain, A.E. Islam, M.A. Alam, “A Comparative Study of Different Physics-Based NBTI Models”, IEEE Trans. Electron Devices, vol. 60, no. 3, pp. 901916, 2013.

S. Gamerith, M. Pölzl, “Negative bias temperature stress in low voltage p-channel DMOS transistors and role of nitrogen”, Microelectron. Reliab., vol. 42, pp. 14391443, 2002.

B.J. Baliga, Fundamentals of Semiconductor Power Devices, New York: Springer, 2008.

V. Benda, J. Gowar, D.A. Grant, Power Semiconductor Devices, New York: John Wiley, 1999.

M.A. Alam, “A Critical Examination of the Mechanisms of Dynamic NBTI for PMOSFETs“, in IEDM Techn. Dig., 2003, pp. 345-348.

R. Fernández, B. Kaczer, A. Nackaerts, S. Demuynck, R. Rodríguez, M. Nafria, G. Groeseneken, “AC NBTI studied in the 1 Hz – 2 GHZ range on dedicated on-chip CMOS circuits”, In IEDM Techn. Dig., 2006, pp. 1-4.

S. Mahapatra, A. E. Islam, S. Deora, V. D. Maheta, K. Joshi, A. Jain, M. A. Alam, “A Critical Reevaluation of the Usefulness of R-D Framework in Predicting NBTI Stress and Recovery”, in Proc. International Reliability Physics Symposium (IRPS), 2011, pp. 614-623.

H. Reisinger, T. Grasser, K. Ermisch, H. Nielen, W. Gustin, C. Schlünder, “Understanding and Modeling AC BTI”, in Proc. International Reliability Physics Symposium (IRPS), 2011, pp. 597-603.

S. Desai, S. Mukhopadhyay, N. Goel, N. Nanaware, B. Jose, K. Joshi, S. Mahapatra, “A Comprehensive AC/DC NBTI Model: Stress, Recovery, Frequency, Duty Cycle and Process Dependence”, In Proc. International Reliability Physics Symposium (IRPS), 2013, pp. XT.2.1 – XT.2.11.

D. Danković, I. Manić, S. Djorić-Veljković, V. Davidović, S. Golubović, N. Stojadinović, “NBT stressinduced degradation and lifetime estimation in p-channel power VDMOSFETs”, Microelectron. Reliab. vol. 46, pp. 1828-1833, 2006.

N. Stojadinović, D. Danković, I. Manić, V. Davidović, S. Djorić-Veljković, S. Golubović, “Impact of negative bias temperature instabilities on lifetime in p-channel power VDMOSFETs”, In Proc. TELSIKS 2007 Conf., 2007, pp. 275-282. [17] N. Stojadinović, D. Danković, I. Manić, A. Prijić, V. Davidović, S. Djorić-Veljković, S. Golubović, Z. Prijić, “Threshold voltage instabilities in p-channel power VDMOSFETs under pulsed NBT stress”, Microelectron. Reliab. vol. 50, pp. 1278-1282, 2010.

I. Manić, D. Danković, A. Prijić, V. Davidović, S. Djorić-Veljković, S. Golubović, Z. Prijić, N. Stojadinović, “NBTI related degradation and lifetime estimation in p-channel power VDMOSFETs under the static and pulsed NBT stress conditions”, Microelectron. Reliab. vol. 51, pp. 1540-1543, 2011.

D. Danković, I. Manić, V. Davidović, A. Prijić, S. Djorić-Veljković, S. Golubović, Z. Prijić, N. Stojadinović, “Lifetime estimation in NBT stressed p-channel power VDMOSFETs”, Facta Universitatis, Series: Automatic Control and Robotics, vol. 11, pp. 15-23, 2012.

I. Manić, D. Danković, A. Prijić, Z. Prijić, N. Stojadinović, “Measurement of NBTI Degradation in pchannel Power VDMOSFETs”, Informacije MIDEM, Journal of Microelectronics, Electronic Components and Materials. vol. 44, pp. 280-287, 2014.

“IRF9520N,” Data sheet, International Rectifier, [Online]. Available: http://www.irf.com/productinfo/datasheets/data/irf9520npbf.pdf

Tektronix, Inc., “High amplitude arbitrary/function generator simplifies measurement in automotive, semiconductor, scientific and industrial applications,” Application Note, [Online]. Available: http://www.tektronix.com/afg3000, 2008.

Agilent Technologies Inc., “Agilent 4156C precision semiconductor parameter analyzer“, Data sheet, p.5. [Online]. Available: http://www.agilent.com, 2009.

A. Prijić, D. Danković, Lj. Vračar, I. Manić, Z. Prijić, N. Stojadinović, “A method for negative bias instability (NBTI) measurements on power VDMOS transistors”, Measure. Sci. and Technol., vol.23, 085003 (8 pp.), 2012.

A. Ortiz-Conde, F.-J. Garcıa Sanchez, J.J. Liou, A. Cerdeira, M. Estrada, Y. Yue, “A review of recent MOSFET threshold voltage extraction methods”, Microelectron. Reliab., vol. 42, pp. 583–596, 2002.

M.A. Alam, “A Critical Examination of the Mechanisms of Dynamic NBTI for PMOSFETs“, In Technical Digest of the IEDM 2003, USA, pp. 345348, 2003.

G. Chen, M.F. Li, C.H. Ang, J.Z. Zheng, D.L. Kwong, “Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling”, IEEE Electron. Dev. Lett., vol. 42, pp. 734–736, 2002. [28] M.F. Li, G. Chen G, C. Shen, X.P. Wang, H.Y. Yu, Y.C Yeo et al., “Dynamic bias temperature instability in ultrathin SiO2 and HfO2 metal-oxide-semiconductor field effect transistor and its impact on device lifetime”, Jpn. J. Appl. Phys., vol. 43(11B), pp. 78077814, 2004.

T. Nigam, “Pulse-stress dependence of NBTI degradation and its impact on circuits”, IEEE Trans. Device Mater. Reliab., vol. 9, pp. 72–78, 2008.

C. Schlunder, R. Brederlow, B. Ankele, W. Gustin, K. Goser, R. Thewes, “Effects of inhomogeneous negative bias temperature stress on p-channel MOSFETs of analogue and RF circuits”, Microelectron. Reliab., vol. 45, pp. 39-46, 2005.

S.S. Tan, T.P. Chen, C.H. Ang, L. Chan, “Mechanism of nitrogen-enhanced negative bias temperature instability in pMOSFET”, Microelectron. Reliab., vol. 45, pp. 19-30, 2005.

M. Ershov, S. Saxena, S. Minehane, P. Clifton, M. Redford, R. Lindley, H. Karbasi, S. Graves, S. Winters, “Degradation dynamics, recovery, and characterization of negative bias temperature instability”, Microelectron. Reliab., vol. 45, pp. 99-105, 2005.

H. Aono, E. Murakami, K. Okuyama, A. Nishida, M. Minami, Y. Ooji, K. Kubota, “Modeling of NBTI saturation effect and its impact on electric field dependence of the lifetime”, Microelectron. Reliab., vol. 45, pp. 1109-1114, 2005.

D. Danković, I. Manić, V. Davidović, S. Djorić-Veljković, S. Golubović, N. Stojadinović, “New Approach in Estimating the Lifetime in NBT Stressed P-Channel Power VDMOSFETs”, In Proc. MIEL 2008 Conference, 2008, pp. 599-602.

N. Stojadinović, D. Danković, S. Djorić-Veljković, V. Davidović, I. Manić, S. Golubović, “Negative bias temperature instability mechanisms in p-channel power VDMOSFETs”, Microelectron. Reliab., vol. 45, pp. 13431348, 2005.

D. Danković, I. Manić, V. Davidović, S. Djorić-Veljković, S. Golubović, N. Stojadinović, “Negative bias temperature instabilities in sequentially stressed and annealed p-channel power VDMOSFETs”, Microelectron. Reliab., vol. 47, pp. 14001405, 2007.

I. Manić, D. Danković, S. Djorić-Veljković, V. Davidović, S. Golubović, N. Stojadinović, “Effects of low gate bias annealing in NBT stressed p-channel power VDMOSFETs”, Microelectron. Reliab., vol. 49, pp. 10031007, 2009.


Refbacks

  • There are currently no refbacks.


ISSN: 0353-3670 (Print)

ISSN: 2217-5997 (Online)

COBISS.SR-ID 12826626