A SYSTEM-ON-CHIP 1.5 GHz PHASE LOCKED LOOP REALIZED USING 40 nm CMOS TECHNOLOGY

Weiyin Wang, Xiangjie Chen, Hei Wong

DOI Number
https://doi.org/10.2298/FUEE1801101W
First page
101
Last page
113

Abstract


This work presents the design and realization of a fully-integrated 1.5 GHz sigma-delta fractional-N ring-based PLL for system-on-chip (SoC) applications. Some design optimizations were conducted to improve the performance of each functional block such as phase frequency detector (PFD), voltage-controlled oscillator (VCO), filter and charge pump (CP) and so as for the whole system. In particular, a time delay circuit is designed for overcoming the blind zone in the PFD; an operational amplifierfeedback structure was used to eliminate the current mismatch in the CP, a 3rd LPF is used for suppressing noises and a current overdrive structure is used in VCO design. The design was realized with a commercial 40 nm CMOS process. The core die sized about 0.041 mm2. Measurement results indicated that the circuit functions well for the locked range between 500 MHz to 1.5 GHz.


Keywords

PLL, blind zone, current mismatch, ring oscillator

Full Text:

PDF

References


V. Ravinuthula and S. Finocchiaro, “A low power high performance PLL with temperature compensated VCO in 65nm CMOS", In Proceedings of the IEEE Radio Frequency Integrated Circuits Symp., 2016, pp. 31-34.

D. Liao, H. Wang, F. F. Dai, Y. Xu, R. Berenguer, “An 802.11 a/b/g/n digital fractional-N PLL with automatic TDC linearity calibration for spur cancellation”, In Proceedings of the IEEE Radio Frequency Integrated Circuits Symp, 2016, pp. 134-137.

S. Ikeda, H. Ito, A. Kasamatsu, Y. Ishikawa, T. Obara, N. Noguchi, et al., “An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique”, In Proceedings of the IEEE Symp. VLSI Circuits, 2016, pp. 1-2.

T. Li X. Fan, and Z. Hua, “CMOS phase frequency detector and charge pump for multi-standard frequency synthesizer”, In Proceedings of the IEEE Int’l Conf. Microwaves, Communications, Antennas and Electronic Systems, 2015, pp. 1-4.

M. Ghasemzadeh, S. Mahdavi, A. Zokaei, and K. Hadidi, “A new adaptive PLL to reduce the lock time in 0.18 μm technology”, In Proceedings of the 23rd International Conference Mixed Design of Integrated Circuits and Systems, 2016, pp. 140-142.

A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, P. K. Hanumolu, “A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider”, IEEE J. Solid-State Circuits, vol. 51, pp. 1771-1784, 2016.

M.-t. Hsieh, J. Welch, G. E. Sobelman, “PLL performance comparison with application to spread spectrum clock generator design,” Analog Integr. Circ. Sig. Process, vol. 63, pp. 197-216, 2010.

A. G. Amer, S. A. Ibrahim, and H. F. Ragai, “A novel current steering charge pump with low current mismatch and variation”, In Proceedings of the IEEE International Symp. Circuits and Systems, 2016, pp. 1666-1669.

S. G. Kim, J. Rhim, D. H. Kwon, M. H. Kim, and W. Y. Choi, “A low-voltage PLL with a current mismatch compensated charge pump”, In Proceedings of the International SoC Design Conference, 2015, pp. 15-16.

M. K. Hati and T. K. Bhattacharyya, “A PFD and Charge Pump switching circuit to optimize the output phase noise of the PLL in 0.13μm CMOS," In Proceedings of the International Conference on VLSI Systems, Architecture, Technology and Applications, 2015, pp. 1-6.

N. Joram, R. Wolf, and F. Ellinger, “High swing PLL charge pump with current mismatch reduction”, Electron. Lett., pp. 661-663, 2014.

Y. He, X. Cui, C. L. Lee, and D. Xue, “An improved fast acquisition PFD with zero blind zone for the PLL application”, In Proceedings of the IEEE International Conference on Electron Devices and SolidState Circuits, 2014, pp. 1-2.

M.-S. Shiau, C.-H. Cheng, H.S. Hsu, H.C. Wu, H.-H. Weng, J.J. Hou, R. C. Sun, “Design for low current mismatch in the CMOS charge pump”, In Proceedings of the International SoC Design Conference, 2013, pp. 310-31.

Analog Devices Totorial MT-086, Fundamentals of phase locked loops (PLLs), Analog Devices, 2009.

W. Wang, X. Chen and H. Wong, “1.5 GHz sigma-delta fractional-N ring-based PLL realized using 40 nm CMOS technology for SoC applications,” In Proceedings of the International Conference on Electronics, Information, and Communications, Phuket, Thailand, January 11-14, 2017.


Refbacks

  • There are currently no refbacks.


ISSN: 0353-3670 (Print)

ISSN: 2217-5997 (Online)

COBISS.SR-ID 12826626