SYNTHESIS OF COMPOSITE LOGIC GATE IN QCA EMBEDDING UNDERLYING REGULAR CLOCKING

Jayanta Pal, Dhrubajyoti Bhowmik, Ayush Ranjan Singh, Apu Kumar Saha, Bibhash Sen

DOI Number
https://doi.org/10.2298/FUEE2101115P
First page
115
Last page
131

Abstract


Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design’s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation.


Keywords

Composite Gate, Regular Clocking, 2-input Symmetric Function, QCA, RES Clocking, Basic Gates, Energy Dissipation

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References


C. S. Lent, P. D. Tougaw, W. Porod, et al., "Quantum cellular automata", Nanotechnology, vol. 4, no. 1, p. 49, 1993.

N. H. Weste and D. Harris, CMOS VLSI design: a circuits and systems perspective. Pearson Education India, 2015.

J. Timler and C. S. Lent, "Power gain and dissipation in quantum-dot cellular automata", J. Appl. Phys., vol. 91, no. 2, pp. 823–831, 2002.

Y. Lu, M. Liu, and C. Lent, "Molecular quantum-dot cellular automata: From molecular structure to circuit dynamics", J. Appl. Phys., vol. 102, no. 3, p. 034311, 2007.

G. L. Snider, A. O. Orlov, I. Amlani, et al., "Quantum-dot cellular automata: Line and majority logic gate", Jpn. J. Appl. Phys., vol. 38, no. 12S, p. 7227, 1999.

S.-S. Ahmadpour, M. Mosleh and S. R. Heikalabad, "The design and implementation of a robust single-layer qca alu using a novel fault-tolerant three-input majority gate", J. Supercomput., vol. 76, pp. 1–31, 2020.

P. D. Tougaw and C. S. Lent, "Logical devices implemented using quantum cellular au- tomata", J. Appl. Phys., vol. 75, no. 3, pp. 1818–1825, 1994.

M. Goswami, M. Roychoudhury, J. Sarkar, et al., "An efficient inverter logic in quantum-dot cellular automata for emerging nanocircuits", Arab. J. Sci. Eng., vol. 45, pp. 1–12, 2019.

C.-K. Wang, I. Yakimenko, I. Zozoulenko, et al., "Dynamical response in an array of quantum-dot cells", J. Appl. Phys., vol. 84, no. 5, pp. 2684–2689, 1998.

Z. Chu, H. Tian, Z. Li, et al., "A high-performance design of generalized pipeline cellular array", IEEE Comput, Archit. Lett., vol. 19, no. 1, pp. 47-50, 2020.

A. Chaudhuri, M. Sultana, D. Sengupta, et al., "A reversible approach to two’s complement addition using a novel reversible tcg gate and its 4 dot 2 electron qca architecture", Microsyst. Technol., vol. 25, no. 5, pp. 1965–1975, 2019.

K. Hennessy and C. S. Lent, "Clocking of molecular quantum-dot cellular automata", J. Vac. Sci. Technol. B: Microelectron. Nanometer Struct. Process. Meas. Phenom, vol. 19, no. 5, pp. 1752–1755, 2001.

M. Goswami, M. R. Choudhury, and B. Sen, "A realistic configurable level triggered flip-flop in quantum-dot cellular automata", In Proceedings of the International Symposium on VLSI Design and Test, 2019, pp. 455–467.

B. Sen, M. Dutta, D. Saran, et al., "An efficient multiplexer in quantum-dot cellular automata", In Proceedings of the Progress in VLSI Design and Test, 2012, pp. 350–351.

Y. Adelnia and A. Rezai, "A novel adder circuit design in quantum-dot cellular automata technology", Int. J. Theor. Phys., vol. 58, no. 1, pp. 184–200, 2019.

H. R. Roshany and A. Rezai, "Novel efficient circuit design for multilayer qca rca", Int. J. Theor. Phys., vol. 58, no. 6, pp. 1745–1757, 2019.

W. Liu, L. Lu, M. O’Neill, et al., "A first step toward cost functions for quantum-dot cellular automata designs", IEEE Trans. Nanotechnol., vol. 13, no. 3, pp. 476–487, 2014.

C. A. T. Campos, A. L. Marciano, O. P. V. Neto, et al., "Use: A universal, scalable, and ef- ficient clocking scheme for qca", IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 35, no. 3, pp. 513–517, 2015.

M. Goswami, A. Mondal, M. H. Mahalat, et al., "An efficient clocking scheme for quantum-dot cellular automata", Int. J. Electron. Lett., vol. 8, no. 1, pp. 83–96, 2019.

V. Vankamamidi, M. Ottavi, and F. Lombardi, "Two-dimensional schemes for clocking/timing of qca circuits", IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 1, pp. 34–44, 2007.

M. Abutaleb, "Robust and efficient quantum-dot cellular automata synchronous counters", Microelectron. J., vol. 61, pp. 6–14, 2017.

M. Raj, L. Gopalakrishnan, and S.-B. Ko, "Design and analysis of novel qca full adder-subtractor", Int. J. Electron. Lett, pp. 1–14, 2020.

R. Singh, S. S. Das, and V. Sarada, "Design of a compact negative-edge triggered t flip-flop in qca technology", J. Electr. Eng. Technol., vol. 11, no. 2, pp. 139–146, 2020.

T. N. Sasamal, A. K. Singh, and A. Mohan, "Design of registers and memory in qca", In Quantum-Dot Cellular Automata Based Digital Logic Circuits: A Design Perspective, pp. 119– 137, 2020.

A. Shiri, A. Rezai, and H. Mahmoodian, "Design of efficient coplanar comparator circuit in qca technology", FU Elec. Energ., vol. 32, no. 1, pp. 119–128, 2019.

M. N. Divshali, A. Rezai, and S. S. F. Hamidpour, "Design of novel coplanar counter circuit in quantum dot cellular automata technology", Int. J. Theor. Phys., vol. 58, no. 8, pp. 2677–2691, 2019.

Z. Taheri, A. Rezai, and H. Rashidi, "Novel single layer fault tolerance rca construction for qca technology", FU Elec. Energ, vol. 32, no. 4, pp. 601–613, 2019.

Y. XianYang and B. Guo, "Further enumerating boolean functions of cryptographic significance", J. Cryptol., vol. 8, no. 3, pp. 115–122, 1995.

D. L. Dietmeyer, "Generating minimal covers of symmetric functions", IEEE Trans. Comput.-Aided Design Integr. Circuits Syst, vol. 12, no. 5, pp. 710–713, 1993.

S. Chakrabarti, S. Das, D. K. Das, et al., "Synthesis of symmetric functions for path-delay fault testability", IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 9, pp. 1076–1081, 2000.

M. Perkowski, P. Kerntopf, A. Buller, et al., "Regular realization of symmetric functions using reversible logic", In Proceedings of the Euromicro Symposium on Digital Systems Design, Warsaw, Poland, 2001, pp. 245-252.

P. K. Bhattacharjee, "Use of symmetric functions designed by qca gates for next generation ic", Int. J. Comput. Theory Eng., vol. 2, no. 2, p. 211, 2010.

B. Sen, M. Dalui, and B. K. Sikdar, "Introducing universal qca logic gate for synthesizing symmetric functions with minimum wire-crossings", In Proceedings of the International Conference and Workshop on Emerging Trends in Technology, 2010, pp. 828–833.

C. S. Lent and P. D. Tougaw, "A device architecture for computing with quantum dots", In Proceedings of the IEEE, vol. 85, no. 4, pp. 541–557, 1997.

P. D. Tougaw and C. S. Lent, "Dynamic behavior of quantum cellular automata", J. Appl. Phys., vol. 80, no. 8, pp. 4722–4736, 1996.

K. Kim, K. Wu and R. Karri, "Quantum-dot cellular automata design guideline", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 89, no. 6, pp. 1607–1614, 2006.

R. Devadoss, K. Paul and M. Balakrishnan, "Clocking-based coplanar wire crossing scheme for qca", In Proceedings of 23rd International Conference on VLSI Design, Bangalore, India, 2010, pp. 339-344.

B. Sen, A. Nag, A. De, et al., "Towards the hierarchical design of multilayer qca logic circuit", J. Comput. Sci., vol. 11, pp. 233–244, 2015.

M. N. Divshali, A. Rezai and A. Karimi, "Towards multilayer QCA SISO shift register based on efficient d-ff circuits", Int. J. Theor. Phys., vol. 57, no. 11, pp. 3326–3339, 2018.

B. Sen, R. Mukherjee, K. Mohit, et al., "Design of reliable universal qca logic in the presence of cell deposition defect", Int. J. Electron., vol. 104, no. 8, pp. 1285–1297, 2017.

B. Sen, M. R. Chowdhury, R. Mukherjee, et al., "Reliability-aware design for programmable qca logic with scalable clocking circuit", J. Comput. Electron., vol. 16, no. 2, pp. 473– 485, 2017.

A. N. Bahar, R. Laajimi, M. Abdullah-Al-Shafi, et al., "Toward efficient design of flip-flops in quantum-dot cellular automata with power dissipation analysis", Int. J. Theor. Phys., vol. 57, no. 11, pp. 3419–3428, 2018.

J. Pal, S. Bhattacharjee, A. K. Saha, et al., "Study on temperature stability and fault tolerance of adder in quantum-dot cellular automata", In Proceedings of the 5th International Conference on Signal Processing, Computing and Control (ISPCC), Solan, India, 2019, pp. 69-74.

M. Dalui, B. Sen, and B. K. Sikdar, "Fault tolerant qca logic design with coupled majority-minority gate", Int. J. Comput. Appl., vol. 1, no. 29, pp. 81–87, 2010.

B. Sen, M. Dutta, D. K. Singh, et al., "Qca multiplexer based design of reversible alu", in IEEE International Conference on Circuits and Systems (ICCAS), Kuala Lumpur, Malaysia, 2012, pp. 168-173.

M. Janez, P. Pecar, and M. Mraz, "Layout design of manufacturable quantum-dot cellular automata", Microelectron. J., vol. 43, no. 7, pp. 501–513, 2012.

Y. Xia and K. Qiu, "Design and application of universal logic gate based on quantum-dot cellular automata", In Proceedings of the 11th IEEE International Conference on Communication Technology, Hangzhou, China, 2008, pp. 335-338.

J. Pal, P. Dutta, and A. K. Saha, "Realization of basic gates using universal gates using quantum-dot cellular automata", In Proceedings of the International Conference on Computing and Communication Systems, 2018, pp. 541–549.

K. Walus, T. J. Dysart, G. A. Jullien, et al., "Qcadesigner: a rapid design and simulation tool for quantum-dot cellular automata", IEEE Trans. Nanotechnol., vol. 3, no. 1, pp. 26–31, 2004.

S. Srivastava, A. Asthana, S. Bhanja, et al., "Qcapro-an error-power estimation tool for qca circuit design", in IEEE international symposium of circuits and systems (ISCAS), Rio de Janeiro, Brazil, 2011, pp. 2377-2380.


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