EVALUATING NBTI AND HCI EFFECTS ON DEVICE RELIABILITY FOR HIGH-PERFORMANCE APPLICATIONS IN ADVANCED CMOS TECHNOLOGIES

Karan Singh, Shruti Kalra, Jyoti Mahur

DOI Number
https://doi.org/10.2298/FUEE2404581S
First page
581
Last page
597

Abstract


The integrated circuit (IC) industry faces significant reliability challenges as MOSFET devices age, particularly at advanced nodes. Key degradation mechanisms include hot-carrier injection (HCI), negative-bias temperature instability (NBTI), and positive-bias temperature instability (PBTI), affecting both PMOS and NMOS transistors. These aging effects alter critical parameters like drain current and threshold voltage, reducing device lifespan. This paper introduces a comprehensive aging framework for MOSFETs, accounting for PBTI, NBTI, and HCI with a focus on partial recovery in AC operations at advanced technology node of 22 nm. A machine learning model enhances feature extraction, while the MOSRA approach accelerates SPICE simulations to optimize yield and reliability.


Keywords

Threshold Voltage, MOSFET, Aging, HCI, Reliability, Temperature

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References


H. Zhang, X. Shi, R. Huang, et al., "Semiconductor memory roadmap: advances in semiconductor memory", IEEE Access, vol. 8, pp. 137566–137590, 2020.

A. Das, X. Wang, C. Hsieh, et al., "Unified aging model of NBTI and HCI degradation towards lifetime prediction for FinFETs at advanced technology nodes", IEEE Trans. Electron Devices, vol. 70, no. 1, pp. 15–22, 2023.

A. Crespo, F. Sanchez, and D. Morente, "Impact of Hot Carrier Injection (HCI) on the reliability of CMOS inverters", IEEE Trans. Device Mater. Reliab., vol. 21, no. 2, pp. 55–64, 2021.

N. Goel and S. Mahapatra, Fundamentals of Bias Temperature Instability in MOS Transistors: Characterization Methods, Process and Materials Impact, DC and AC Modeling. Springer, 2022, pp. 209–263.

H. Gupta, Y. Wang, and H. Lin, "Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection", in Proceedings of the IEEE Conference Publications, 2022, pp. 131–138.

A. Das and T. Mogami, "An Accurate and Scalable MOSFET Aging Model for Circuit Simulation", IEEE Trans. Device Mater. Reliab., vol. 22, no. 4, pp. 390–396, 2021.

Fraunhofer IIS/EAS, "White Paper: Circuit Level Aging Simulations", Fraunhofer Institute for Integrated Circuits, 2023. (Available: www.eas.iis.fraunhofer.de).

S. Reddy and J. Liu, "Reliability Challenges in FinFETs", Springer, 2021, pp. 123-139. (Available: www.springerlink.com).

S. Mahapatra, N. Goel, and A. Islam, "Fundamentals of Bias Temperature Instability in MOS Transistors: Characterization Methods, Process and Materials Impact, DC and AC Modeling", in Fundamentals of Bias Temperature Instability in MOS Transistors, Springer, 2022, pp. 209–263.

H. Gupta, Y. Wang, and H. Lin, "Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection", in Proceedings of the IEEE Conference Publications, 2022, pp. 131–138.

A. Das and T. Mogami, "An Accurate and Scalable MOSFET Aging Model for Circuit Simulation", IEEE Trans. Device Mater. Reliab., vol. 22, no. 4, pp. 390–396, 2021.

L. Chen and M. Tahoori, "MOSRA: An efficient and versatile MOS aging modeling and reliability analysis solution for 45 nm and below", in Proceedings of the IEEE Conference Publications, 2011, pp. 1–5.

A. Torres-Jacome and E. Tlelo-Cuautle, "On the Prediction of the Threshold Voltage Degradation in CMOS Technology Due to Bias-Temperature Instability", Electronics, vol. 7, no. 12, pp. 427–435, 2018.

N.D. Arora and M.S. Sharma, "MOSFET substrate current model for circuit simulation”, IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1392–1398, 1991.

B. Tudor, J. Wang, Z. Chen, R. Tan, W. Liu, F. Lee, "An accurate MOSFET aging model for 28 nm integrated circuit simulation", Microelectronics Reliability, vol. 52, no. 8, pp. 1565–1570, 2012.

T. Grasser, H. Reisinger, B. Kaczer, W. Goes, H. Reisinger, T. Aichinger, P. Hehenberger, P.J. Wagner, F. Schanovsky, J. Franco, M. T. Luque, and M. Nelhiebel, "The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction-Diffusion to Switching Oxide Traps", IEEE Trans. Electron Devices, vol. 58, no. 11, pp. 3652–3666, 2011.

N. Parihar, N. Goel, S. Mukhopadhyay, and S. Mahapatra, "BTI analysis tool: Modeling of NBTI DC, AC stress and recovery time kinetics, nitrogen impact, and EOL estimation", IEEE Trans. Electron Devices, vol. 65, no. 2, pp. 392–403, 2017.

C. Pan and S. Paul, "Reliability Analysis of MOSFETs under Temperature and Voltage Cycling Stress", Microelectronics Reliability, vol. 76, pp. 29–38, 2017.

Y. Liang, X. Li, S. George, S. Srinivasa, Z. Zhu, S. K Gupta, S. Datta, V. Narayanan, "Influence of body effect on sample-and-hold circuit design using negative capacitance FET", IEEE Trans. Electron Devices, vol. 65, no. 9, pp. 3909–3914, 2018.

H. Ramezani, S. Alavi, and M. Niakan, "Unified Cumulative Stress Model Integrating HCI and BTI for Nanoscale MOSFETs", Solid-State Electronics, vol. 174, p. 107863, 2020.

Y. Chen, Z. Li, and J. Zhou, "Machine Learning-Assisted Aging Prediction for MOSFET Reliability", IEEE Trans. Device Mater. Reliab., vol. 20, no. 4, pp. 500–508, 2020.

J. Ghosh, "Efficient machine learning-assisted failure analysis method for circuit-level defect prediction”, Machine Learning with Applications, vol. 16, p. 100537, 2024.

F. Hosseinabadi, S. Chakraborty, S.K. Bhoi, G. Prochart, D. Hrvanovic, O. Hegazy, "A Comprehensive Overview of Reliability Assessment Strategies and Testing of Power Electronics Converters", IEEE Open J. Power Electron., 2024.

A. Campos-Cruz, G. Espinosa-Flores-Verdad, A. Torres-Jacome, and E. Tlelo-Cuautle, "On the prediction of the threshold voltage degradation in CMOS technology due to bias-temperature instabilityv, Electronics, vol. 7, no. 12, p. 427, 2018.

B. Tudor, J. Wang, Z. Chen, R. Tan, W. Liu, and F. Lee, "An accurate and scalable MOSFET aging model for circuit simulation", in Proc. 2011 12th Int. Symp. Quality Electron. Design, pp. 1–4, 2011.

M.F. Li, S.J. Rhee, and C. Choi, "Dynamic Bias-Temperature Instability in Ultrathin SiO₂ and HfO₂ MOSFETs and Its Impact on Device Lifetime", Jpn. J. Appl. Phys., vol. 43, pp. 7807–7814, 2004.

Synopsys, "MOS Device Aging Analysis with HSPICE and CustomSim”, Synopsys Technical Documentation, 2023.

W. Wang, S. Yang, S. Bhardwaj, S. Vrudhula, F. Liu, and Y. Cao, "The impact of NBTI effect on combinational circuit: Modeling, simulation, and analysis", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 173–183, 2009.


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